ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 191
ORSPI4-2FTE1036I
Manufacturer Part Number
ORSPI4-2FTE1036I
Description
FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
Manufacturer
Lattice
Datasheet
1.ORSPI4-2FTE1036I.pdf
(263 pages)
Specifications of ORSPI4-2FTE1036I
Product Category
FPGA - Field Programmable Gate Array
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
FPTBGA-1036
Minimum Operating Temperature
- 40 C
Factory Pack Quantity
60
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Lattice Semiconductor
Supported Data Rates
The Memory Controller on the ORSPI4 device can support the following data rates.
Table 74. Supported Data Rates (36-Bit QDR-II, 32 bit Considered Data)
1. Data Rate = (Max. write data rate + Max. read data rate) for 32 bits of data.
2. Characterized with 200 Mhz rated QDR-II SRAM devices with their DLL enabled. Duty cycle of PMIC and PMICN signals was close to 50%.
3. Assumes board trace lengths of 3 inches or less.
Memory Controller Input/Output Timing Specification
Figure 99. Memory Controller Output Timing Specifications
Table 75. Memory Controller Output Timing Specifications
Clock Frequency (DDR)
D
Symbol
PMIK(N)
t
t
t
t
av
dv
ai
di
156 MHz
PMIK to previous address invalid
PMIK to address valid
PMIK to previous data invalid
PMIK to data valid
PMIK/PMINKN duty cycle
-1
Data Rate
19.97 Gbps
Description
1, 2
PMIKN
PMID
PMIA
PMIK
3
Clock Frequency (DDR) Data Rate
165 MHz
Data Rate
T
T
191
-2
ai
di
D
T
T
av
dv
PMIK(N)
21.12 Gbps
Min Value
2.65
40%
1.2
2.0
1.0
1, 2
3
Clock Frequency (DDR)
ORCA ORSPI4 Data Sheet
175 MHz
Max Value
60%
–
–
–
–
-3
PMIK/PMIKN
Data Rate
22.40 Gbps
Clock Cycle
Units
ns
ns
ns
ns
1, 2
3
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