ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 39

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Table 4. SPIA Core Transmit FPGA Interface in 128-Bit Mode (Continued)
Note: For SPIB replace A with B
DPRAM
Status
Misc.
I/Os
I/Os
Lattice Semiconductor
0
SPIA_TX128_EOP
SPIA_TX128_ERR
SPIA_TX128_WE
SPIA_TX128_PORT[7:0]
SPIA_TX128_WD_CNT_RST FPGA → Core Line Write Termination indicator. This signal causes the FIFO write address
SPIA_TX128_LINK_DIS_0
SPIA_TX128_CLK
SPIA_TX128_FIFO_FULL
SPIA_TX128_PORT_ID[7:0]
SPIA_TX128_STAT[1:0]
SPIA_TX128_BURST_VAL[3:
0]
ATREFCLK_F
SPIA_TREFCLK_X8
SPI_SATM_A
FPGA Interface I/Os
FPGA → Core Packet error indication. A '1' indicates an error has occurred for the current
FPGA → Core Write Enable. A logic '1' causes data on the SPIA_TX128_DATA_0[127:0]
FPGA → Core SPI4 port indicator, used to associate the current transmit data with a par-
FPGA → Core Link disable control signal. When asserted to a logic '1', the AMA will cease
FPGA → Core Transmit write reference clock. There is a single clock per SPI4 interface
Core →FPGA FIFO full status. The status is given in response to the assertion of any
Core →FPGA Port number of the currently serviced SPI4 data port. The value can either
Core →FPGA Status of the SPI4 port currently being serviced. These signals can be
Core →FPGA Indicates the number of SPI4 cycles for which the currently active port will
Core →FPGA Transmit reference clock. This clock signal is 1/4th the SPI4 clock. This sig-
FPGA → Core Quarter-rate Transmit reference clock. This FPGA-sourced clock reference
FPGA → Core ‘0’ - Incoming ATSCLK is assumed to be edge-aligned with the data and
FPGA → Core
Direction
From/To
End of Packet indicator. A '1' indicates the end of packet for a particular
port.
When an EOP is detected by the DPRAM Write Pointer Logic, the address
pointer will be automatically incremented to the next location within the
FIFO partition range.
packet being transmitted. The ERR signal must be asserted coincident with
the EOP signal.
bus to be captured for a write to the DPRAM.
ticular port number.
pointer within the embedded core to increment to the next address location
for the addressed partition. This signal can be used for custom applications
as well as for diagnostic test functions.
polling from a DPRAM. All ports associated with a disabled DPRAM will
remain unserviced until the control signal is deasserted. The AMA will send
IDLE data across the SPI4 link. If the application continues to write data to
that port FIFO, it will eventually fill and provide proper FIFO fill status to the
application.
when operating in 128-bit mode.
valid address on the SPIA_TX128_ADDR[2:0] bus. This signal will be
asserted to a logic '1' when the current FIFO partition has crossed the con-
figured fill level within the partition.
be the actual SPI4 value or a programmed user value. Further details are
provided in the TX Calendar Control Logic description.
used in conjunction with the SPIA_TX32_PORT_ID signal to police trans-
mit traffic congestion for a particular SPI4 port.
be serviced. Each cycle indicates an attempt to read 128 bits of data from
the respective FIFO partition.
nal can be used to synchronize FPGA application logic to the FPSC logic.
must be 2x the desired Transmit SPI4 line clock rate. When not operating
the Transmit SPI4 core in Quarter-rate mode, this signal should be tied off.
Ex: For a 100 MHz Transmit SPI4 line clock, SPIA_TREFCLK_X8 from the
FPGA must be 200 MHz.
centered to the data eye within the chip.
‘1’ - Incoming ATSCLK is assumed to be skewed with respect to the data
off-chip.
39
Description
ORCA ORSPI4 Data Sheet