DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 10

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–10
Table 1–14. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications
Table 1–15. Single-Ended SSTL and HSTL I/O Standards Signal Specifications
Stratix III Device Handbook, Volume 2
SSTL-2
CLASS I, II
SSTL-18
CLASS I, II
SSTL-15
CLASS I, II
HSTL-18
CLASS I, II
HSTL-15
CLASS I, II
HSTL-12
CLASS I, II
SSTL-2
CLASS I
SSTL-2
CLASS II
SSTL-18
CLASS I
SSTL-18
CLASS II
SSTL-15
CLASS I
SSTL-15
CLASS II
HSTL-18
CLASS I
HSTL-18
CLASS II
HSTL-15
CLASS I
HSTL-15
CLASS II
HSTL-12
CLASS I
Standard
Standard
I/O
I/O
-0.15
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
2.375
1.425
1.425
Min
1.71
1.71
1.14
V
IL(DC)
V
V
V
V
V
V
Refer to the figure in “Single-Ended Voltage Referenced I/O Standard” in the
“Glossary” on page 1–326
explanation of terms used in
V
V
V
V
V
V
(V)
REF
REF
REF
REF
CCIO
REF
Typ
2.5
1.8
1.5
1.8
1.5
1.2
REF
REF
REF
REF
REF
REF
Max
-0.125
-0.125
- 0.15
- 0.15
-0.08
(V)
-0.1
-0.1
-0.1
-0.1
-0.1
-0.1
2.625
1.575
1.575
Max
1.89
1.89
1.26
V
V
V
V
V
V
V
V
V
V
V
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
Min
+0.125
+0.125
+0.15
+0.15
+0.08
+0.1
+0.1
+0.1
+0.1
+0.1
+0.1
0.49 * V
0.47 * V
0.47 * V
V
0.833
IH(DC)
0.85
0.68
Min
(V)
V
V
V
V
V
V
V
V
V
V
V
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
Max
+ 0.15
+ 0.3
+ 0.3
+ 0.3
+ 0.3
+ 0.3
+ 0.3
+ 0.3
+ 0.3
+ 0.3
+ 0.3
for voltage referenced receiver input waveform and
0.5 * V
0.5 * V
0.5 * V
Table
V
0.75
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
REF
Typ
0.9
0.9
V
V
V
V
V
V
V
(V)
V
V
V
V
V
REF
REF
REF
REF
REF
REF
REF
CCIO
CCIO
CCIO
IL(AC)
REF
REF
REF
REF
Max
1–14.
-0.175
-0.175
- 0.31
- 0.31
-0.25
-0.25
-0.15
-0.2
-0.2
-0.2
-0.2
(V)
0.51 * V
0.53 * V
0.53 * V
0.969
V
V
Max
0.95
V
V
V
V
V
0.9
V
V
V
V
V
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
IH(AC)
Min
+ 0.175
+ 0.175
+ 0.31
+ 0.31
+ 0.15
+ 0.25
+ 0.25
+ 0.2
+ 0.2
+ 0.2
+ 0.2
CCIO
CCIO
CCIO
(Note 1)
(V)
VTT - 0.57
VTT - 0.76 VTT + 0.76
0.25* V
0.2 * V
0.2 * V
0.47 * V
V
V
V
0.475
(Part 1 of 2)
VTT -
REF
REF
Max
0.28
OL
0.4
0.4
0.4
0.4
Min
—
—
—
- 0.04
- 0.04
(V)
CCIO
CCIO
CCIO
CCIO
© July 2010 Altera Corporation
VTT + 0.57
0.75 * V
V
0.8 * V
0.8 * V
V
V
V
V
CCIO
V
VTT +
0.475
CCIO
CCIO
CCIO
CCIO
V
Min
OH
TT
V
V
V
Electrical Characteristics
- 0.28
Typ
V
V
V
- 0.4
- 0.4
- 0.4
- 0.4
CCIO
CCIO
CCIO
(V)
(V)
REF
REF
REF
CCIO
CCIO
/2
/2
/2
CCIO
(mA)
16.2 -16.2
13.4 -13.4
IOL
8.1
6.7
16
16
16
0.53 * V
V
V
8
8
8
8
REF
REF
Max
—
—
—
+ 0.04
+ 0.04
(mA)
-8.1
-6.7
-16
-16
-16
I
-8
-8
-8
-8
CCIO
OH