DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 246

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–246
Table 1–115. EP3SE80 Column Pins Input Timing Parameters (Part 3 of 3)
Table 1–116. EP3SE80 Row Pins Input Timing Parameters (Part 1 of 3)
Stratix III Device Handbook, Volume 2
DIFFERENTIAL
2.5-V SSTL
CLASS I
DIFFERENTIAL
2.5-V SSTL
CLASS II
LVDS
MINI-LVDS
RSDS
DIFFERENTIAL
1.2-V HSTL
CLASS I
DIFFERENTIAL
1.2-V HSTL
CLASS II
I/O Standard
I/O Standard
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Table 1–116
standards.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
h
h
h
h
h
h
Industrial
Industrial
-0.840
-0.855
-0.840
-0.855
-0.944
-0.691
-0.944
-0.691
-0.944
-0.691
-0.749
-0.893
-0.749
-0.893
0.969
1.117
0.969
1.117
1.077
0.961
1.077
0.961
1.077
0.961
0.875
1.156
0.875
1.156
Fast Model
lists the EP3SE80 row pins input timing parameters for differential I/O
Fast Model
Commercial
Commercial
-0.881
-0.857
-0.881
-0.857
-0.979
-0.700
-0.979
-0.700
-0.979
-0.700
-0.794
-0.894
-0.794
-0.894
1.028
1.142
1.028
1.142
1.130
0.989
1.130
0.989
1.130
0.989
0.936
1.174
0.936
1.174
-1.289 -1.395 -1.518 -1.460 -1.828 -1.394 -1.510 -1.459 -1.866
-1.350 -1.525 -1.683 -1.603 -1.505 -1.534 -1.696 -1.613 -1.554
-1.289 -1.395 -1.518 -1.460 -1.828 -1.394 -1.510 -1.459 -1.866
-1.350 -1.525 -1.683 -1.603 -1.505 -1.534 -1.696 -1.613 -1.554
-1.054 -1.015 -1.154 -1.107 -1.454 -0.975 -1.107 -1.061 -1.493
-1.502 -1.818 -1.968 -1.871 -1.796 -1.862 -2.019 -1.921 -1.844
-1.054 -1.015 -1.154 -1.107 -1.454 -0.975 -1.107 -1.061 -1.493
-1.502 -1.818 -1.968 -1.871 -1.796 -1.862 -2.019 -1.921 -1.844
-1.054 -1.015 -1.154 -1.107 -1.454 -0.975 -1.107 -1.061 -1.493
-1.502 -1.818 -1.968 -1.871 -1.796 -1.862 -2.019 -1.921 -1.844
-1.145 -1.244 -1.343 -1.291 -1.633 -1.246 -1.344 -1.293 -1.677
-1.447 -1.639 -1.828 -1.736 -1.666 -1.644 -1.834 -1.741 -1.709
-1.145 -1.244 -1.343 -1.291 -1.633 -1.246 -1.344 -1.293 -1.677
-1.447 -1.639 -1.828 -1.736 -1.666 -1.644 -1.834 -1.741 -1.709
1.493
1.771
1.493
1.771
1.288
1.951
1.288
1.951
1.288
1.951
1.345
1.864
1.345
1.864
1.1 V
1.1 V
V
V
C2
C2
CCL
CCL
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
=
=
1.625
1.998
1.625
1.998
1.285
2.328
1.285
2.328
1.285
2.328
1.468
2.104
1.468
2.104
1.1 V
1.1 V
V
V
C3
C3
CCL
CCL
=
=
1.769
2.207
1.769
2.207
1.447
2.533
1.447
2.533
1.447
2.533
1.587
2.344
1.587
2.344
1.1 V
1.1 V
V
V
C4
C4
CCL
CCL
=
=
1.697
2.097
1.697
2.097
1.389
2.408
1.389
2.408
1.389
2.408
1.524
2.224
1.524
2.224
1.1 V
1.1 V
V
V
CCL
CCL
=
=
C4L
C4L
2.070
2.011
2.070
2.011
1.737
2.342
1.737
2.342
1.737
2.342
1.867
2.163
1.867
2.163
0.9 V
0.9 V
V
V
CCL
CCL
=
=
© July 2010 Altera Corporation
1.633
2.016
1.633
2.016
1.257
2.387
1.257
2.387
1.257
2.387
1.479
2.120
1.479
2.120
1.1 V
V
1.1 V
V
CCL
I3
I3
CCL
=
=
1.772
2.232
1.772
2.232
1.412
2.599
1.412
2.599
1.412
2.599
1.597
2.362
1.597
2.362
1.1 V
1.1 V
V
V
CCL
I4
I4
CCL
=
=
I/O Timing
1.706
2.116
1.706
2.116
1.355
2.472
1.355
2.472
1.355
2.472
1.535
2.240
1.535
2.240
1.1 V
1.1 V
V
V
CCL
CCL
=
=
I4L
I4L
2.109
2.062
2.109
2.062
1.777
2.394
1.777
2.394
1.777
2.394
1.912
2.210
1.912
2.210
0.9 V
0.9 V
V
V
CCL
CCL
=
=
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns