DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 17

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Switching Characteristics
Table 1–21. DSP Block Performance Specifications for Stratix III Devices
© July 2010 Altera Corporation
99-bit multiplier (a, c, e, g)
99-bit multiplier (b, d, f, h)
1212-bit multiplier (a, e)
1212-bit multiplier (b, d, f, h)
1818-bit multiplier
3636-bit multiplier
Double mode
1818-bit multiply adder
1818-bit multiply adder
1818-bit multiply adder with loop
back
1818-bit multiply adder with loop
back
1818-bit multiply accumulator
1818-bit multiply adder with
chainout
Input Cascade Independent output
of four 1818 bit multiplier
36-bit shift (32 bit data)
Notes to
(1) Maximum is for a fully pipelined block with Round and Saturation disabled.
(2) The DSP block implements eight independent 9b9b multiplies using a, b, c, d for the top DSP half block and e, f, g, h for the bottom DSP half block
(3) The DSP block implements six independent 12b12b multiplies using a, b, d for the top DSP half block and e, f, h for the bottom DSP half block multipliers.
(4) Maximum for loopback input registers disabled, Round and Saturation disabled, pipeline and output registers enabled.
(5) The F
multipliers.
(4)
Table
max
for the EP3SL200, EP3SE260, and EP3SL340 devices at the C2 speed grade is 7% slower than the C2 values shown in the table.
Mode
1–21:
DSP Block Specifications
Table 1–21
(3)
(2)
(2)
(3)
Multipliers
Number of
lists the Stratix III DSP block performance specifications.
1
1
1
1
1
1
1
2
4
2
2
4
4
4
1
C2
V
1.1 V
440
500
440
500
600
440
440
490
490
490
390
475
475
550
475
CCL
(5)
=
V
1.1 V
365
410
365
410
495
365
365
405
405
405
320
390
390
455
390
C3
CCL
=
V
1.1 V
315
375
315
375
440
315
315
345
345
345
300
330
330
415
330
C4
CCL
=
(Note 1)
V
1.1 V
315
375
315
375
440
315
315
345
345
345
240
330
330
415
330
CCL
=
C4L
0.9 V
V
240
270
240
270
320
220
220
250
250
250
180
240
240
270
250
CCL
Stratix III Device Handbook, Volume 2
=
1.1 V
V
345
385
345
385
470
345
345
380
380
380
300
370
370
430
370
I3
CCL
=
1.1 V
V
315
375
315
375
440
315
315
345
345
345
300
330
330
415
330
I4
CCL
=
1–17
0.9 V
V
225
250
225
250
300
205
205
235
235
235
135
225
225
250
235
I4L
CCL
=
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz