DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 298

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–298
Table 1–134. EP3SE260 Row Pins Output Timing Parameters (Part 5 of 5)
Table 1–135. EP3SE260 Column Pins Input Timing Parameters (Part 1 of 3)
Stratix III Device Handbook, Volume 2
1.2-V
HSTL
CLASS I
3.0-V PCI
3.0-V
PCI-X
LVDS
MINI-LVDS
RSDS
DIFFERENTIAL
1.2-V HSTL
CLASS I
Standard
I/O Standard
I/O
4mA
6mA
8mA
—
—
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
PLL
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
PLL
PLL
Table 1–135
EP3SE260 devices for differential I/O standards.
Table 1–135
I/O standards.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
t
t
t
t
t
t
t
t
t
t
co
co
co
co
co
co
co
co
co
co
Industrial
-1.153
-0.824
-1.153
-0.824
-1.161
-0.816
-1.161
-0.816
1.289
1.103
1.289
1.103
1.297
1.095
1.297
1.095
Industrial
3.478
1.379
3.466
1.367
3.463
1.364
3.542
1.476
3.542
1.476
Fast Model
through
lists the EP3SE260 column pins input timing parameters for differential
Fast Model
Commercial
-1.221
-0.821
-1.221
-0.821
-1.233
-0.809
-1.233
-0.809
1.376
1.122
1.376
1.122
1.388
1.110
1.388
1.110
Commercial
Table 1–138
3.726
1.586
3.714
1.578
3.712
1.578
3.812
1.661
3.812
1.661
-1.879 -1.911 -2.067 -1.987 -2.459 -1.928 -2.084 -1.987 -2.459
-1.403 -1.493 -1.659 -1.580 -1.562 -1.493 -1.659 -1.580 -1.562
-1.879 -1.911 -2.067 -1.987 -2.459 -1.928 -2.084 -1.987 -2.459
-1.403 -1.493 -1.659 -1.580 -1.562 -1.493 -1.659 -1.580 -1.562
-1.889 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475
-1.393 -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546
-1.889 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475
-1.393 -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546
2.114
1.882
2.114
1.882
2.124
1.872
2.124
1.872
1.1 V
V
C2
CCL
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
=
5.501 5.718 6.296 6.118 6.538 5.883 6.420 6.118 6.538
2.036 2.128 2.323 2.308 2.266 2.231 2.457 2.308 2.266
5.490 5.706 6.284 6.109 6.529 5.872 6.411 6.109 6.529
2.027 2.119 2.314 2.296 2.254 2.220 2.448 2.296 2.254
5.494 5.711 6.290 6.118 6.538 5.878 6.421 6.118 6.538
2.034 2.127 2.323 2.302 2.260 2.226 2.458 2.302 2.260
5.520 5.723 6.294 6.113 6.564 5.875 6.437 6.113 6.564
2.049 2.137 2.343 2.368 2.264 2.253 2.476 2.368 2.264
5.520 5.723 6.294 6.113 6.564 5.875 6.437 6.113 6.564
2.049 2.137 2.343 2.368 2.264 2.253 2.476 2.368 2.264
1.1 V
V
C2
CCL
list the maximum I/O timing parameters for
=
2.150
1.986
2.150
1.986
2.161
1.975
2.161
1.975
1.1 V
V
C3
CCL
1.1 V
V
=
C3
CCL
=
2.330
2.207
2.330
2.207
2.346
2.191
2.346
2.191
1.1 V
V
C4
CCL
1.1 V
V
C4
CCL
=
=
2.237
2.099
2.237
2.099
2.253
2.083
2.253
2.083
1.1 V
V
1.1 V
V
CCL
CCL
=
=
C4L
C4L
2.711
2.096
2.711
2.096
2.727
2.080
2.727
2.080
0.9 V
0.9 V
V
V
CCL
CCL
=
=
© July 2010 Altera Corporation
1.1 V
V
2.177
1.998
2.177
1.998
2.188
1.987
2.188
1.987
1.1 V
V
CCL
I3
CCL
I3
=
=
1.1 V
V
I4
CCL
2.355
2.217
2.355
2.217
2.370
2.202
2.370
2.202
1.1 V
V
=
I4
CCL
=
I/O Timing
1.1 V
V
CCL
2.237
2.099
2.237
2.099
2.253
2.083
2.253
2.083
1.1 V
V
=
CCL
I4L
=
0.9 V
V
I4L
CCL
=
2.711
2.096
2.711
2.096
2.727
2.080
2.727
2.080
0.9 V
V
CCL
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns