DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 244

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–244
Table 1–114. EP3SE80 Row Pins Output Timing Parameters (Part 5 of 5)
Table 1–115. EP3SE80 Column Pins Input Timing Parameters (Part 1 of 3)
Stratix III Device Handbook, Volume 2
1.2-V
HSTL
CLASS I
3.0-V PCI
3.0-V
PCI-X
LVDS
MINI-LVDS
RSDS
DIFFERENTIAL
1.2-V HSTL
CLASS I
Standard
I/O Standard
I/O
4mA
6mA
8mA
—
—
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
PLL
PLL
Table 1–115
EP3SE80 devices for differential I/O standards.
Table 1–115
I/O standards.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
t
t
t
t
t
t
t
t
t
t
co
co
co
co
co
co
co
co
co
co
Industrial
-0.997
-0.691
-0.997
-0.691
-0.997
-0.691
-0.813
-0.882
1.133
0.960
1.133
0.960
1.133
0.960
0.942
1.144
Industrial
3.081
1.260
3.072
1.251
3.071
1.250
3.177
1.333
3.177
1.333
through
lists the EP3SE80 column pins input timing parameters for differential
Fast Model
Fast Model
Commercial
-1.029
-0.701
-1.029
-0.701
-1.029
-0.701
-0.852
-0.886
1.184
0.994
1.184
0.994
1.184
0.994
0.999
1.171
Commercial
Table 1–118
3.316
1.434
3.308
1.426
3.308
1.426
3.415
1.510
3.415
1.510
-1.181 -1.169 -1.324 -1.269 -1.645 -1.133 -1.542 -1.230 -1.683
-1.428 -1.714 -1.834 -1.749 -1.648 -1.756 -1.968 -1.795 -1.697
-1.181 -1.169 -1.324 -1.269 -1.645 -1.133 -1.542 -1.230 -1.683
-1.428 -1.714 -1.834 -1.749 -1.648 -1.756 -1.968 -1.795 -1.697
-1.181 -1.169 -1.324 -1.269 -1.645 -1.133 -1.542 -1.230 -1.683
-1.428 -1.714 -1.834 -1.749 -1.648 -1.756 -1.968 -1.795 -1.697
-1.258 -1.368 -1.483 -1.423 -1.794 -1.368 -1.482 -1.428 -1.837
-1.383 -1.555 -1.721 -1.641 -1.544 -1.563 -1.729 -1.645 -1.588
1.415
1.879
1.415
1.879
1.415
1.879
1.460
1.802
1.1 V
V
C2
CCL
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
=
4.684 5.077 5.577 5.446 5.723 5.195 5.696 5.566 5.800
1.844 1.931 2.129 2.150 2.191 2.031 2.233 2.252 2.179
4.675 5.068 5.568 5.437 5.714 5.186 5.687 5.557 5.791
1.835 1.922 2.120 2.141 2.182 2.022 2.224 2.243 2.170
4.682 5.076 5.577 5.446 5.723 5.195 5.697 5.567 5.801
1.842 1.930 2.129 2.150 2.191 2.031 2.234 2.253 2.180
4.724 5.106 5.581 5.466 5.731 5.228 5.698 5.590 5.810
1.860 1.936 2.152 2.143 2.217 2.038 2.252 2.248 2.208
4.724 5.106 5.581 5.466 5.731 5.228 5.698 5.590 5.810
1.860 1.936 2.152 2.143 2.217 2.038 2.252 2.248 2.208
1.1 V
V
list the maximum I/O timing parameters for
C2
CCL
=
1.436
2.224
1.436
2.224
1.436
2.224
1.595
2.025
1.1 V
V
C3
CCL
1.1 V
=
V
C3
CCL
=
1.618
2.401
1.618
2.401
1.618
2.401
1.731
2.242
1.1 V
V
C4
CCL
1.1 V
V
=
C4
CCL
=
1.551
2.288
1.551
2.288
1.551
2.288
1.659
2.134
1.1 V
V
CCL
1.1 V
V
=
CCL
C4L
=
C4L
1.927
2.194
1.927
2.194
1.927
2.194
2.031
2.045
0.9 V
V
CCL
0.9 V
V
CCL
=
© July 2010 Altera Corporation
=
1.411
2.277
1.411
2.277
1.411
2.277
1.604
2.042
1.1 V
V
1.1 V
V
CCL
I3
I3
CCL
=
=
1.858
2.567
1.858
2.567
1.858
2.567
1.739
2.260
1.1 V
1.1 V
V
V
CCL
I4
CCL
I4
=
=
I/O Timing
1.1 V
V
1.524
2.345
1.524
2.345
1.524
2.345
1.674
2.147
1.1 V
V
CCL
CCL
=
=
I4L
I4L
0.9 V
V
1.966
2.245
1.966
2.245
1.966
2.245
2.075
2.091
0.9 V
CCL
V
CCL
=
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns