DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 326

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–326
Glossary
Table 1.
Stratix III Device Handbook, Volume 2
Glossary Table (Part 1 of 4)
Letter
A
B
C
D
E
F
G
H
I
Differential I/O
Standards
f
H S D R D P A
Subject
f
f
H S C L K
H S D R
—
—
—
—
—
—
—
The following table lists the glossary for this chapter.
Receiver Input Waveforms
Transmitter Output Waveforms
High-Speed I/O Block: High-speed receiver/transmitter input and output clock frequency.
High-Speed I/O Block: Maximum/minimum LVDS data transfer rate
(f
High-Speed I/O Block: Maximum/minimum LVDS data transfer rate
(f
H S D R
H S D R D P A
= 1/TUI), non-DPA.
Single-Ended Waveform
Differential Waveform
Single-Ended Waveform
Differential Waveform
= 1/TUI), DPA.
V
V
CM
CM
V
V
OD
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
ID
V
V
OD
ID
Definitions
—
—
—
—
—
—
—
V
V
OD
ID
p − n = 0 V
p − n = 0 V
Positive Channel (p) = V
Negative Channel (n) = V
Ground
Positive Channel (p) = V
Negative Channel (n) = V
Ground
© July 2010 Altera Corporation
OH
IH
OL
IL
Glossary