DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 180

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–180
Table 1–93. EP3SL340 Column Pins Output Timing Parameters (Part 1 of 7)
Stratix III Device Handbook, Volume 2
3.3-V
LVTTL
3.3-V
LVCMOS
3.0-V
LVTTL
Standard
I/O
4mA
8mA
12mA
16mA
4mA
8mA
12mA
16mA
4mA
8mA
12mA
16mA
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Table 1–93
I/O standards.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
Industrial Commercial
lists the EP3SL340 column pins output timing parameters for single-ended
3.705
4.269
3.638
4.202
3.552
4.116
3.545
4.110
3.711
4.275
3.556
4.120
3.563
4.127
3.547
4.111
3.669
4.232
3.558
4.125
3.522
4.087
3.504
4.068
Fast Model
3.705
4.269
3.638
4.202
3.552
4.116
3.545
4.110
3.711
4.275
3.556
4.120
3.563
4.127
3.547
4.111
3.669
4.232
3.558
4.125
3.522
4.087
3.504
4.068
5.372 5.559
6.214 6.409
5.263 5.448
6.105 6.298
5.160 5.350
6.001 6.200
5.143 5.322
5.985 6.172
5.377 5.564
6.218 6.414
5.170 5.367
6.012 6.217
5.164 5.346
6.006 6.196
5.141 5.320
5.983 6.171
5.339 5.528
6.181 6.377
5.209 5.394
6.053 6.246
5.146 5.325
5.987 6.174
5.117 5.297
5.959 6.147
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1.1 V
V
C2
CCL
=
1.1 V
V
C3
CCL
=
6.083 5.935
6.992 6.812
5.970 5.822
6.879 6.699
5.878 5.730
6.789 6.609
5.837 5.689
6.747 6.567
6.090 5.942
7.000 6.820
5.889 5.741
6.799 6.619
5.863 5.715
6.775 6.595
5.834 5.686
6.746 6.566
6.050 5.902
6.983 6.803
5.912 5.765
6.867 6.688
5.838 5.691
6.803 6.624
5.810 5.662
6.780 6.601
1.1 V
V
C4
CCL
=
1.1 V
V
CCL
=
C4L
6.364 5.559 6.083 5.935 6.364
7.355 6.409 6.992 6.812 7.355
6.251 5.448 5.970 5.822 6.251
7.242 6.298 6.879 6.699 7.242
6.159 5.350 5.878 5.730 6.159
7.152 6.200 6.789 6.609 7.152
6.118 5.322 5.837 5.689 6.118
7.110 6.172 6.747 6.567 7.110
6.371 5.564 6.090 5.942 6.371
7.363 6.414 7.000 6.820 7.363
6.170 5.367 5.889 5.741 6.170
7.162 6.217 6.799 6.619 7.162
6.144 5.346 5.863 5.715 6.144
7.138 6.196 6.775 6.595 7.138
6.115 5.320 5.834 5.686 6.115
7.109 6.171 6.746 6.566 7.109
6.331 5.528 6.050 5.902 6.331
7.346 6.377 6.983 6.803 7.346
6.193 5.394 5.912 5.765 6.193
7.229 6.246 6.867 6.688 7.229
6.119 5.325 5.838 5.691 6.119
7.165 6.174 6.803 6.624 7.165
6.091 5.297 5.810 5.662 6.091
7.142 6.147 6.780 6.601 7.142
0.9 V
V
CCL
© July 2010 Altera Corporation
=
1.1 V
V
CCL
I3
=
1.1 V
V
CCL
I4
=
I/O Timing
1.1 V
V
CCL
=
I4L
0.9 V
V
CCL
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns