DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 6

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–6
Table 1–6. Bus Hold Parameters for Stratix III Devices (Part 2 of 2)
Table 1–7. On-Chip Termination Calibration Accuracy Specifications for Stratix III Devices
Stratix III Device Handbook, Volume 2
High overdrive
current
Bus-hold trip
point
25- R
3.3, 3.0, 2.5, 1.8, 1.5, 1.2
50- R
3.3, 3.0, 2.5, 1.8, 1.5, 1.2
50- R
20-R
3.3, 3.0, 2.5, 1.8, 1.5, 1.2
25- R
R
Notes to
(1) OCT calibration accuracy is valid at the time of calibration only.
(2) 25-
(3) 1.5 V and 1.2 V only supports 40-
(4) For resistance tolerance after power-up calibration, refer to
OCT_CAL
Parameter

S
S
T
S
S _left_shift
Table
(2)
2.5, 1.8, 1.5, 1.2
to 60-R
R
S
Symbol
not supported for 1.5 V and 1.2 V in Row I/O.
1–7:
Symbol
S
V
I
ODH
TRIP
On-Chip Termination (OCT) Specifications
If you enable OCT calibration, calibration is automatically performed at power-up for
the I/Os connected to the calibration block.
calibration block accuracy specifications.
0V <V
Conditions
Internal series termination with
calibration (25- setting)
Internal series termination with
calibration (50- setting)
Internal parallel termination with
calibration (50- setting)
Expanded range for internal
series termination with
calibration
(Between 20- to 60-setting)
Internal left shift series
termination with calibration
(25- R
Internal series termination with
calibration

—
IN
to 60-
<V
CCIO
S _left_shift

Description
expanded range.
Min
0.45
—
setting)
1.2 V
Max
-120
0.95
Equation 1–1
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Min
0.50
—
1.5 V
and
V
3.3, 3.0, 2.5, 1.8, 1.5, 1.2 V
V
3.3, 3.0, 2.5, 1.8, 1.5, 1.2 V
V
V
3.3, 3.0, 2.5, 1.8, 1.5, 1.2 V
(3)
V
3.3, 3.0, 2.5, 1.8, 1.5, 1.2 V
Max
-160
1.00
CCIO
CCIO
CCIO
CCIO
CCIO
Table 1–9 on page
=
=
= 2.5, 1.8, 1.5, 1.2 V
=
=
Table 1–7
Min
0.68
Conditions
—
1.8 V
V
CCIO
Max
-200
1.07
1–8.
lists the Stratix III OCT
Min
0.70
(Note 1)
—
2.5 V
(4)
© July 2010 Altera Corporation
Max
-300
1.70
±10
±10
±10
C2
±8
±8
Calibration
Accuracy
Electrical Characteristics
3.0 V/3.3 V
Min
0.80
±10
±10
±10
—
C3,
±8
±8
I3
Max
-500
2.00
±10
±10
±10
C4,
±8
±8
I4
Unit
Unit
µA
%
%
%
%
%
V