DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 221

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–106. EP3SE50 Row Pins Input Timing Parameters (Part 3 of 3)
Table 1–107. EP3SE50 Column Pins Output Timing Parameters (Part 1 of 4)
© July 2010 Altera Corporation
DIFFERENTIAL
2.5-V SSTL
CLASS II
LVDS_E_1R
LVDS_E_3R
MINI-
LVDS_E_1R
MINI-
LVDS_E_3R
RSDS_E_1R
RSDS_E_3R
I/O Standard
I/O Standard
Clock
GCLK
GCLK
PLL
—
—
—
—
—
—
Table 1–107
I/O standards.
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
t
t
t
t
PLL
PLL
PLL
PLL
PLL
PLL
su
su
h
h
Industrial Commercial
-0.762
-0.796
0.878
1.049
t
t
t
t
t
t
t
t
t
t
t
t
co
co
co
co
co
co
co
co
co
co
co
co
Fast Model
lists the EP3SE50 column pins output timing parameters for differential
Industrial Commercial
3.058
3.054
3.058
3.054
3.058
3.054
3.085
3.075
3.075
3.068
3.067
3.089
-0.796
-0.789
0.925
1.053
Fast Model
3.277
3.280
3.277
3.280
3.277
3.280
3.310
3.300
3.300
3.294
3.292
3.314
-1.128 -1.227 -1.336 -1.287 -1.561 -1.231 -1.336 -1.290 -1.593
-1.341 -1.533 -1.709 -1.620 -1.638 -1.530 -1.710 -1.620 -1.688
1.314
1.742
1.1 V
V
C2
CCL
=
1.436
1.984
4.610 5.014 5.527 5.385 5.614 5.140 5.654 5.514 5.680
4.657 5.069 5.589 5.447 5.676 5.199 5.720 5.580 5.746
4.610 5.014 5.527 5.385 5.614 5.140 5.654 5.514 5.680
4.657 5.069 5.589 5.447 5.676 5.199 5.720 5.580 5.746
4.610 5.014 5.527 5.385 5.614 5.140 5.654 5.514 5.680
4.657 5.069 5.589 5.447 5.676 5.199 5.720 5.580 5.746
4.681 5.092 5.611 5.469 5.698 5.220 5.740 5.600 5.766
4.671 5.081 5.601 5.459 5.688 5.209 5.730 5.590 5.756
4.674 5.085 5.605 5.463 5.692 5.214 5.735 5.595 5.761
4.667 5.079 5.599 5.457 5.686 5.207 5.729 5.589 5.755
4.664 5.076 5.596 5.454 5.683 5.204 5.725 5.585 5.751
4.685 5.096 5.615 5.473 5.702 5.224 5.745 5.605 5.771
1.1 V
1.1 V
V
V
C3
C2
CCL
CCL
=
=
1.1 V
V
1.569
2.216
1.1 V
V
C3
CCL
C4
CCL
=
=
1.1 V
V
C4
1.505
2.094
CCL
1.1 V
V
CCL
=
=
C4L
1.1 V
V
CCL
1.780
2.120
0.9 V
Stratix III Device Handbook, Volume 2
V
=
CCL
C4L
=
0.9 V
V
CCL
1.451
1.991
=
1.1 V
V
I3
CCL
=
1.1 V
V
I3
CCL
=
1.580
2.226
1.1 V
V
CCL
I4
1.1 V
V
=
I4
CCL
=
1.518
2.103
1.1 V
1–221
V
CCL
1.1 V
V
=
CCL
I4L
=
I4L
1.813
2.172
0.9 V
V
0.9 V
V
CCL
CCL
=
=
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns