DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 294

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–294
Table 1–133. EP3SE260 Column Pins Output Timing Parameters (Part 7 of 7)
Table 1–134. EP3SE260 Row Pins Output Timing Parameters (Part 1 of 5)
Stratix III Device Handbook, Volume 2
1.2-V
HSTL
CLASS I
1.2-V
HSTL
CLASS II
3.0-V PCI
3.0-V
PCI-X
3.3-V
LVTTL
Standard
Standard
I/O
I/O
4mA
6mA
8mA
10mA
12mA
16mA
—
—
4mA
8mA
12mA
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Table 1–134
I/O standards.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
Industrial
Industrial
3.491
3.934
3.483
3.926
3.484
3.927
3.473
3.916
3.473
3.916
3.494
3.937
3.597
4.040
3.597
4.040
3.648
1.582
3.555
1.489
3.456
1.390
lists the EP3SE260 row pins output timing parameters for single-ended
Fast Model
Fast Model
Commercial
Commercial
3.524
3.923
3.516
3.915
3.517
3.916
3.506
3.905
3.506
3.905
3.527
3.926
3.630
4.029
3.630
4.029
3.902
1.785
3.797
1.680
3.707
1.574
5.175
5.810
5.166
5.801
5.174
5.809
5.161
5.796
5.161
5.796
5.177
5.812
5.222
5.857
5.222
5.857
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1.1 V
V
5.663 5.865 6.484 6.256 6.709 6.063 6.530 6.256 6.709
2.228 2.322 2.505 2.489 2.454 2.441 2.632 2.489 2.454
5.533 5.727 6.340 6.112 6.565 5.922 6.414 6.112 6.565
2.098 2.184 2.361 2.346 2.310 2.300 2.483 2.346 2.310
5.414 5.604 6.212 5.995 6.446 5.795 6.315 5.995 6.446
1.979 2.061 2.233 2.250 2.182 2.173 2.354 2.250 2.182
1.1 V
V
C2
CCL
C2
CCL
=
=
5.343
6.027
5.334
6.018
5.342
6.026
5.329
6.013
5.329
6.013
5.344
6.028
5.378
6.062
5.378
6.062
1.1 V
V
1.1 V
V
C3
CCL
C3
CCL
=
=
5.945
6.592
5.928
6.583
5.924
6.592
5.901
6.578
5.902
6.579
5.980
6.592
5.955
6.617
5.955
6.617
1.1 V
1.1 V
V
V
C4
CCL
C4
CCL
=
=
1.1 V
5.728
6.420
5.719
6.411
5.728
6.420
5.714
6.406
5.715
6.407
5.728
6.420
5.753
6.445
5.753
6.445
V
1.1 V
V
CCL
CCL
=
=
C4L
C4L
0.9 V
V
6.150
6.994
6.141
6.977
6.150
6.973
6.136
6.950
6.137
6.951
6.150
7.029
6.175
7.004
6.175
7.004
0.9 V
V
CCL
CCL
=
© July 2010 Altera Corporation
=
1.1 V
V
5.343
6.027
5.334
6.018
5.342
6.026
5.329
6.013
5.329
6.013
5.344
6.028
5.378
6.062
5.378
6.062
CCL
I3
1.1 V
V
CCL
I3
=
=
1.1 V
V
I4
CCL
5.945
6.592
5.928
6.583
5.924
6.592
5.901
6.578
5.902
6.579
5.980
6.592
5.955
6.617
5.955
6.617
1.1 V
V
=
CCL
I4
=
I/O Timing
1.1 V
V
CCL
5.728
6.420
5.719
6.411
5.728
6.420
5.714
6.406
5.715
6.407
5.728
6.420
5.753
6.445
5.753
6.445
1.1 V
V
=
CCL
I4L
=
I4L
0.9 V
V
CCL
6.150
6.994
6.141
6.977
6.150
6.973
6.136
6.950
6.137
6.951
6.150
7.029
6.175
7.004
6.175
7.004
0.9 V
V
=
CCL
=
Units
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns