DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 202
![KIT DEVELOPMENT STRATIX III](/photos/9/20/92079/dk-dev-3sl150n_sml.jpg)
DK-DEV-3SL150N
Manufacturer Part Number
DK-DEV-3SL150N
Description
KIT DEVELOPMENT STRATIX III
Manufacturer
Altera
Series
Stratix® IIIr
Type
FPGAr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.DK-DEV-3SL150N.pdf
(34 pages)
Specifications of DK-DEV-3SL150N
Contents
Development Platform, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP3S
Silicon Family Name
Stratix III
Kit Contents
Development Board, Cable And Accessories
Rohs Compliant
Yes
For Use With/related Products
EP3SL150F152
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2568
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-3SL150N
Manufacturer:
Altera
Quantity:
135
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1–202
Table 1–99. EP3SL340 Column Pin Delay Adders for Regional Clock
Table 1–100. EP3SL340 Row Pin Delay Adders for Regional Clock
Table 1–101. EP3SE50 Column Pins Input Timing Parameters (Part 1 of 4)
Stratix III Device Handbook, Volume 2
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
3.3-V LVTTL
3.3-V
LVCMOS
Standard
I/O
Parameter
Parameter
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
t
t
t
t
Table 1–99
must be added to the GCLK values. Use these adder values to determine I/O timing
when the I/O pin is driven using the regional clock. This applies to all I/O standards
supported by Stratix III devices.
Table 1–99
Table 1–100
EP3SE50 I/O Timing Parameters
Table 1–101
EP3SE50 devices for single-ended I/O standards.
Table 1–101
I/O standards.
t
t
t
t
su
su
su
su
h
h
h
h
Industrial
Industrial
-0.341
0.318
2.716
-0.052
-0.157
-2.36
0.075
0.157
Industrial
-0.743
-1.037
-0.743
-1.037
0.870
1.290
0.870
1.290
Fast Model
Fast Model
Fast Model
and
lists the EP3SL340 column pin delay adders when using the regional clock.
lists the EP3SL340 row pin delay adders when using the regional clock.
through
lists the EP3SE50 column pins input timing parameters for single-ended
Commercial
Commercial
-0.107
-2.128
0.171
2.739
Commercial
Table 1–100
-0.066
-0.139
0.079
0.151
-0.742
-1.037
-0.742
-1.037
0.869
1.290
0.869
1.290
Table 1–104
-3.344 -3.384 -3.571 -3.487 -3.545 -3.246 -3.636 -3.357 -3.544
0.255
4.379
1.1 V
V
-0.18
-0.107 -0.098 -0.127 -0.129 -0.282 -0.082 -0.118 -0.085 -0.285
-0.232 -0.248 -0.272 -0.259 -0.422 -0.252 -0.256 -0.244 -0.444
1.1 V
0.133
0.262
V
C2
-1.063 -1.165 -1.374 -1.329 -1.605 -1.165 -1.374 -1.329 -1.605
-1.466 -1.593 -1.830 -1.772 -2.038 -1.593 -1.830 -1.772 -2.038
-1.063 -1.165 -1.374 -1.329 -1.605 -1.165 -1.374 -1.329 -1.605
-1.466 -1.593 -1.830 -1.772 -2.038 -1.593 -1.830 -1.772 -2.038
CCL
1.241
1.836
1.241
1.836
C2
CCL
1.1 V
V
list the EP3SL340 regional (RCLK) clock adder values that
C2
=
CCL
=
=
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
-0.169 -0.171 -0.167 -0.362
0.247
4.508
list the maximum I/O timing parameters for
1.1 V
V
0.124
0.274
1.1 V
V
C3
1.366
2.009
1.366
2.009
CCL
1.1 V
C3
V
CCL
C3
CCL
=
=
=
0.257
4.926
1.1 V
V
0.125
0.306
1.1 V
V
C4
CCL
1.595
2.292
1.595
2.292
1.1 V
C4
V
CCL
C4
CCL
=
=
=
0.244
4.717
1.1 V
V
0.124
0.288
1.1 V
V
CCL
1.538
2.207
1.538
2.207
1.1 V
CCL
V
=
CCL
=
C4L
=
C4L
C4L
0.369
5.376
0.9 V
V
0.307
0.464
0.9 V
V
CCL
1.815
2.484
1.815
2.484
0.9 V
CCL
V
=
CCL
=
=
© July 2010 Altera Corporation
4.508
-0.03
1.1 V
V
0.37
0.117
0.268
1.1 V
V
I3
CCL
1.366
2.009
1.366
2.009
I3
CCL
1.1 V
V
=
CCL
I3
=
=
-0.043 -0.034 -0.287
0.253
1.1 V
V
4.94
0.116
0.291
1.1 V
V
CCL
I4
1.595
2.292
1.595
2.292
CCL
I4
1.1 V
V
=
CCL
I4
=
=
0.232
1.1 V
V
4.89
0.117
0.278
I/O Timing
1.1 V
V
CCL
1.538
2.207
1.538
2.207
CCL
1.1 V
V
=
CCL
=
I4L
=
I4L
0.336
5.434
I4L
0.9 V
V
0.9 V
V
0.31
0.46
CCL
CCL
1.815
2.484
1.815
2.484
0.9 V
V
=
CCL
=
=
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
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