DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 36

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–36
Table 1–37. Output Timing Measurement Methodology for Output Pins (Part 3 of 3)
I/O Default Capacitive Loading
Stratix III Device Handbook, Volume 2
MINI-LVDS_E_1R
MINI-LVDS_E_3R
RSDS_E_1R
RSDS_E_3R
Notes to
(1) Hyper transport is not supported by Stratix III devices.
(2) LVPECL outputs are not supported by Stratix III devices.
(3) You can change the Quartus II timing conditions using the Advanced I/O Timing feature.
(4) V
(5) Terminated I/O standards require an additional 30 mV IR drop on V
(6) Terminated I/O standards require an additional 50 mV IR drop on V
I/O Standard
CC
is nominally 1.1 V less 50 mV (1.05 V).
Table
1–37:
Table 1–38
Table 1–38. Default Loading of Various I/O Standards for Stratix III Devices (Part 1 of 2)
3.3-V LVTTL
3.3-V LVCMOS
3.0-V LVTTL
3.0-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVTTL/LVCMOS
3.0-V PCI
3.0-V PCI-X
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.2-V HSTL
Differential SSTL-2 CLASS I
Differential SSTL-2 CLASS II
Differential SSTL-18 CLASS I
120
120
—
—
R
S
100
100
100
100
R
lists the default capacitive loading of various I/O standards.
D
—
—
—
—
R
T
Loading and Termination
120
170
120
170
I/O Standard
R
P
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
2.325
2.325
2.325
2.325
CC
CCIO
V
(1.02 V).
CCIO
and V
CCPD
2.325
2.325
2.325
2.325
V
.
CCPD
1.02
1.02
1.02
1.02
V
CC
V
—
—
—
—
TT
© July 2010 Altera Corporation
C
Capacitive
L
(pF)
0
0
0
0
Load
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Measurement
V
1.1625
1.1625
1.1625
1.1625
Point
MEAS
I/O Timing
Unit
(v)
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF