DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 312

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–312
.
Table 1–148. EP3SL70 Column Pin Global Clock Timing Specifications
Table 1–149. EP3SL70 Row Pin Global Clock Timing Specifications
Table 1–150. EP3SL70 Column Pin Regional Clock Timing Specifications
Table 1–151. EP3SL70 Row Pin Regional Clock Timing Specifications
Stratix III Device Handbook, Volume 2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Parameter
Parameter
Parameter
Parameter
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
Industrial
Industrial
Industrial
Industrial
-0.012
-0.012
-0.031
-0.011
-0.011
-0.064
1.749
1.749
1.732
1.650
0.051
1.689
1.689
1.637
1.555
0.018
Fast Model
Fast Model
Fast Model
Fast Model
EP3SL70 Clock Timing Parameters
Table 1–148
devices.
Table 1–150
devices.
Commercial
Commercial
Commercial
Commercial
-0.021
-0.021
-0.022
-0.022
-0.006
1.735
1.735
1.840
1.749
0.115
0.024
1.689
1.689
1.726
1.635
0.085
and
and
Table 1–149
Table 1–151
-0.255 -0.306 -0.251
-0.255 -0.306 -0.251
-0.144 -0.219 -0.193
-0.286 -0.382 -0.374
-0.261 -0.308 -0.256
-0.261 -0.308 -0.256
-0.176 -0.252 -0.230
-0.318 -0.415 -0.411
2.434
2.434
2.524
2.382
2.388
2.388
2.353
2.211
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C2
C2
C2
C2
CCL
CCL
CCL
CCL
=
=
=
=
2.702
2.702
2.758
2.595
2.649
2.649
2.566
2.403
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C3
C3
C3
C3
CCL
CCL
CCL
CCL
list the global clock timing specifications for EP3SL70
list the regional clock timing parameters for EP3SL70
=
=
=
=
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
3.056
3.056
3.083
2.902
3.004
3.004
2.885
2.704
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C4
C4
C4
C4
CCL
CCL
CCL
CCL
=
=
=
=
-0.203
-0.203
-0.144
-0.315
-0.207
-0.207
-0.180
-0.351
2.950
2.950
2.986
2.815
2.723
2.723
2.786
2.615
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
C4L
C4L
C4L
C4L
-0.044
-0.044
-0.188
-0.347
-0.054
-0.054
-0.226
-0.385
3.403
3.403
3.227
3.068
3.132
3.132
2.964
2.805
0.9 V
0.9 V
0.9 V
0.9 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
-0.306
-0.306
-0.170
-0.340
-0.308
-0.308
-0.203
-0.373
2.702
2.702
2.811
2.641
2.649
2.649
2.625
2.455
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
I3
CCL
I3
CCL
I3
CCL
I3
CCL
=
=
=
=
© July 2010 Altera Corporation
3.056
3.056
0.161
0.161
3.157
2.968
0.275
0.086
3.014
3.014
0.224
0.224
2.948
2.759
0.307
0.118
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
I4
CCL
I4
CCL
I4
CCL
I4
CCL
=
=
=
=
-0.203 -0.044
-0.203 -0.044
-0.097 -0.234
-0.276 -0.393
-0.207 -0.054
-0.207 -0.054
-0.139 -0.272
-0.318 -0.431
2.950
2.950
3.042
2.863
2.723
2.723
2.839
2.660
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
I4L
I4L
I4L
I4L
I/O Timing
3.403
3.403
3.260
3.101
3.132
3.132
3.001
2.842
0.9 V
0.9 V
0.9 V
0.9 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
Units
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns