DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 314

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–314
Table 1–156. EP3SL110 Column Pin Regional Clock Timing Specifications
Table 1–157. EP3SL110 Row Pin Regional Clock Timing Specifications
.
Table 1–158. EP3SL110 Column Pin Periphery Clock Timing Specifications
Table 1–159. EP3SL110 Row Pin Periphery Clock Timing Specifications
Stratix III Device Handbook, Volume 2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Parameter
Parameter
Parameter
Parameter
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
Industrial
Industrial
Industrial
Industrial
-0.036
-0.036
-0.074
-0.029
-0.029
-0.067
1.689
1.689
1.684
1.602
0.008
1.541
1.541
1.430
1.348
0.015
Fast Model
Fast Model
Fast Model
Fast Model
Table 1–156
devices.
Table 1–158
devices.
Commercial
Commercial
Commercial
Commercial
-0.038
-0.038
-0.020
-0.031
-0.031
-0.019
1.687
1.687
1.792
1.701
0.071
1.538
1.538
1.503
1.412
0.072
and
and
Table 1–157
Table 1–159
-0.262 -0.317 -0.278
-0.262 -0.317 -0.278
-0.189 -0.276 -0.218
-0.334 -0.439 -0.399
-0.253 -0.310 -0.276
-0.253 -0.310 -0.276
-0.188 -0.267 -0.219
-0.333 -0.430 -0.400
2.360
2.360
2.440
2.298
2.257
2.257
2.156
2.011
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C2
C2
C2
C2
CCL
CCL
CCL
CCL
=
=
=
=
2.600
2.600
2.644
2.481
2.539
2.539
2.416
2.253
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C3
C3
C3
C3
CCL
CCL
CCL
CCL
list the regional clock timing parameters for EP3SL110
list the periphery clock timing parameters for EP3SL110
=
=
=
=
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
2.924
2.924
2.985
2.804
2.931
2.931
2.783
2.602
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C4
C4
C4
C4
CCL
CCL
CCL
CCL
=
=
=
=
-0.239
-0.239
-0.188
-0.359
-0.222
-0.222
-0.180
-0.351
2.836
2.836
2.879
2.708
2.810
2.810
2.665
2.494
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
C4L
C4L
C4L
C4L
-0.020
-0.020
-0.214
-0.373
-0.020
-0.020
-0.214
-0.373
3.241
3.241
3.044
2.885
3.345
3.345
2.926
2.767
0.9 V
0.9 V
0.9 V
0.9 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
-0.317
-0.317
-0.209
-0.379
-0.310
-0.310
-0.206
-0.376
2.600
2.600
2.720
2.550
2.539
2.539
2.465
2.295
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
I3
CCL
I3
CCL
I3
CCL
I3
CCL
=
=
=
=
© July 2010 Altera Corporation
-0.278
-0.278
-0.174
-0.363
-0.276
-0.276
-0.170
-0.359
2.924
2.924
3.044
2.855
2.931
2.931
2.828
2.639
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
I4
CCL
I4
CCL
I4
CCL
I4
CCL
=
=
=
=
-0.239 -0.020
-0.239 -0.020
-0.141 -0.263
-0.320 -0.422
-0.222 -0.020
-0.222 -0.020
-0.133 -0.263
-0.312 -0.422
2.836
2.836
2.938
2.759
2.810
2.810
2.711
2.532
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
I4L
I4L
I4L
I4L
I/O Timing
3.241
3.241
3.083
2.924
3.345
3.345
2.951
2.792
0.9 V
0.9 V
0.9 V
0.9 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
Units
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns