DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 30

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–30
Table 1–34. On-Chip Termination Calibration Block Specification
I/O Timing
Timing Model
Stratix III Device Handbook, Volume 2
OCTUSRCLK
t
t
t
OCTCAL
OCTSHIFT
RS_RT
Symbol
Clock required by OCT calibration blocks
Number of OCTUSRCLK clock cycles required
for OCT Rs and Rt calibration
Number of OCTUSRCLK clock cycles required
for OCT code to shift out per OCT calibration block
Time required to dynamically switch from Rs to Rt
OCT Calibration Block Specifications
Table 1–34
devices.
DCD Specifications
Table 1–35
Table 1–35. Duty Cycle Distortion on Stratix III I/O Pins
The following sections describe the timing models, preliminary and final timings, I/O
timing measurement methodology, I/O default capacitive loading, programmable
IOE delay, programmable output buffer delay, user I/O timing, and dedicated clock
pin timing.
The DirectDrive technology and MultiTrack interconnect ensure predictable
performance, accurate simulation, and accurate timing analysis across all Stratix III
device densities and speed grades. This section describes the performance of the
Stratix III device I/Os.
All specifications except the fast model are representative of worst-case supply
voltage and junction temperature conditions. Fast model specifications are
representative of best case process, supply voltage, and junction temperature
conditions.
The timing numbers listed in this section are extracted from the Quartus II software
version 8.1.
Output Duty Cycle
Note to
(1) The DCD specification applies to clock outputs from the PLLs, global clock tree, and IOE driving dedicated and
general-purpose I/O pins.
Table
lists the on-chip termination calibration block specifications for Stratix III
lists the worst case duty cycle distortion for Stratix III devices.
1–35:
Symbol
Description
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Min
45
C2
Max
55
(Note 1)
Min
45
C3
Min
Max
—
—
—
—
55
© July 2010 Altera Corporation
Typical
Min
1000
45
2.5
—
28
C4
Max
55
Max
20
—
—
—
I/O Timing
cycles
cycles
Unit
MHz
Unit
%
ns