DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 31

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Preliminary and Final Timing
I/O Timing Measurement Methodology
© July 2010 Altera Corporation
Timing models can have either preliminary or final status. The Quartus II software
issues an informational message during design compilation if the timing models are
preliminary.
Preliminary status means that the timing models are subject to change in future
Quartus II releases. Initially, timing numbers are created using simulation results,
process data, and other known parameters. Parts of the timing models may be
correlated to silicon measurements. Various tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing models are based on simulation models that are characterized versus the
actual device measurements under all allowable operating conditions. When the
timing models are final, all or most of the Stratix III family devices have been
completely characterized and no further changes to the timing model are expected.
Table 1–36. Timing Model Status for Stratix III Devices
Altera characterizes timing delays at the worst-case process, minimum voltage, and
maximum temperature for input register setup time (t
Quartus II software uses the following equations to calculate t
Stratix III devices input signals.
t
+ data delay from the input pin to the input register
+ micro setup time of the input register
- clock delay from the input pin to the input register
t
- data delay from the input pin to the input register
+ micro hold time of the input register
+ clock delay from the input pin to the input register
su
h
EP3SL50
EP3SL70
EP3SL110
EP3SL150
EP3SL200
EP3SL340
EP3SE50
EP3SE80
EP3SE110
EP3SE260
=
=
Table 1–36
Device
lists the status of the Stratix III device timing models.
Preliminary
—
—
—
—
—
—
—
—
—
—
su
) and hold time (t
Stratix III Device Handbook, Volume 2
su
and t
h
timing for the
h
Final
). The
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