DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 18

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–18
Table 1–22. TriMatrix Memory Block Performance Specifications for Stratix III Devices
Stratix III Device Handbook, Volume 2
MLAB
M9K
Memory
Block
Type
(2)
Single port 16 × 10
Simple dual-port 16 20
ROM 64 × 10
ROM 32 × 20
Single-port 8K × 1
Single-port 4K × 2 or 2K × 4
Single-port 1K × 9, 512 × 18, or
256 × 36
Simple dual-port, 8K × 1
Simple dual-port, 4K × 2 or 2K × 4
Simple dual-port, 1K × 9, 512 × 18,
or 256 × 36
Simple dual-port, 8K × 1, 4K × 2 or
2K × 4 with
read-during-write option set to Old
Data
Simple dual-port, 1K × 9, 512 × 18,
256 × 36 with read-during-write
option set to Old Data
True dual-port, 8K × 1
True dual-port, 4K × 2 or 2K × 4
True dual-port, 1K × 9 or 512 × 18
True dual-port, 8K × 1, 4K × 2, or
2K × 4 with
read-during-write option set to Old
Data
True dual-port, 1K × 9 or 512 × 18
with
read-during-write option set to Old
Data
ROM 1P, 8K × 1, 4K × 2, or 2K × 4
ROM 1P, 1K × 9, 512 × 18, or
256 × 36
ROM 2P, 8K × 1, 4K × 2, or 2K × 4
ROM 2P, 1K × 9, or 512 × 18
Min Pulse Width (Clock High Time)
Min Pulse Width (Clock Low Time)
TriMatrix Memory Block Specifications
Table 1–22
Mode
lists the Stratix III TriMatrix Memory Block specifications.
ALUTs
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TriMatrix
Memory
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
C2
1.1 V
V
600
600
600
600
550
575
565
545
570
565
375
375
530
550
545
350
340
580
575
580
575
800
500
CCL
(6)
=
V
1.1 V
1000
500
500
500
500
465
485
475
460
480
475
312
312
440
460
460
295
285
485
485
485
485
625
C3
CCL
=
V
1.1 V
1100
450
450
450
450
390
405
395
385
400
395
265
265
370
245
240
405
405
405
405
690
385
380
C4
CCL
(Note 1)
=
V
1.1 V
1100
450
450
450
450
390
405
395
385
400
395
265
265
370
385
380
245
240
405
405
405
405
690
CCL
=
C4L
© July 2010 Altera Corporation
(Part 1 of 3)
0.9 V
V
1800
1100
340
340
370
340
245
255
245
240
250
245
205
200
230
240
235
175
165
260
255
265
260
CCL
Switching Characteristics
=
1.1 V
V
1000
475
475
475
475
440
460
450
435
455
450
295
295
420
280
270
460
460
460
460
625
435
435
I3
CCL
=
1.1 V
V
1100
450
450
450
450
390
405
395
385
400
395
265
265
370
385
380
245
240
405
405
405
405
690
I4
CCL
=
0.9 V
V
1800
1100
I4L
320
320
350
320
230
230
220
225
225
220
185
180
215
215
210
160
150
235
230
240
235
CCL
=
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps