DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 331
DK-DEV-3SL150N
Manufacturer Part Number
DK-DEV-3SL150N
Description
KIT DEVELOPMENT STRATIX III
Manufacturer
Altera
Series
Stratix® IIIr
Type
FPGAr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.DK-DEV-3SL150N.pdf
(34 pages)
Specifications of DK-DEV-3SL150N
Contents
Development Platform, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP3S
Silicon Family Name
Stratix III
Kit Contents
Development Board, Cable And Accessories
Rohs Compliant
Yes
For Use With/related Products
EP3SL150F152
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2568
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-3SL150N
Manufacturer:
Altera
Quantity:
135
- Current page: 331 of 332
- Download datasheet (4Mb)
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Chapter Revision History
Table 1–202. Chapter Revision History (Part 2 of 2)
© July 2010 Altera Corporation
July 2008
May 2008
November 2007
October 2007
May 2007
May 2007
March 2007
November 2006
Date
Version
1.3
1.2
1.1
1.7
1.6
1.5
1.4
1.0
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Added new contact information table to the About this Handbook section.
Updated Table 1–44 through Table 1–205.
Added I/O Timing section.
Initial Release.
Updated “Operating Conditions” introduction section.
Updated Table 1–3, Table 1–7, Table 1–8, Table 1–19, Table 1–21,
Table 1–22, Table 1–25, Table 1–26,Table 1–28, Table 1–29, Table 1–30,
Table 1–31, Table 1–32, Table 1–33, Table 1–35, and Table 1–48.
Updated “PLL Specifications” introduction section.
Updated “I/O Timing Measurement Methodology” section.
Updated Figure 1–5, Figure 1–6, and Figure 1–7.
Updated all tables for timing section.
Added “Internal Weak Pull-Up Resistor” section.
Removed “Stratix III Temperature Sensing Diode Specifications” section.
Added Figure 1–6 and Figure 1–7.
Added derating factors Table 1–45 and Table 1–46.
Updated Table 1–90 to Table 1–109.
Updated Table 1–140 to Table 1–149.
Updated Table 1–175 to Table 1–180.
Updated Table 1–181 to Table 1–186.
Updated Table 1–205 to Table 1–210.
Updated I/O Timing
Added new device packages for EP3SL50, EP3SL110, EP3SE80.
Changes Made
Stratix III Device Handbook, Volume 2
1–331
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