DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 68

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–68
Table 1–51. EP3SL70 Column Pins Input Timing Parameters (Part 3 of 3)
Table 1–52. EP3SL70 Row Pins Input Timing Parameters (Part 1 of 3)
Stratix III Device Handbook, Volume 2
1.2-V HSTL
CLASS I
1.2-V HSTL
CLASS II
3.0-V PCI
3.0-V
PCI-X
3.3-V LVTTL
3.3-V
LVCMOS
3.0-V LVTTL
Standard
Standard
I/O
I/O
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Table 1–52
standards.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
h
h
h
h
h
h
Industrial
Industrial
-0.732
-0.885
-0.720
-0.873
-0.720
-0.873
-0.823
-0.976
-0.811
-0.688
-0.811
-0.688
-0.817
-0.682
0.856
1.138
0.844
1.126
0.844
1.126
0.945
1.227
0.925
0.937
0.925
0.937
0.931
0.931
Fast Model
Fast Model
lists the EP3SL70 row pins input timing parameters for single-ended I/O
Commercial
Commercial
-0.731
-0.885
-0.719
-0.873
-0.719
-0.873
-0.822
-0.976
0.856
1.138
0.844
1.126
0.844
1.126
0.945
1.227
-0.836
-0.684
-0.836
-0.684
-0.847
-0.673
0.962
0.945
0.962
0.945
0.973
0.934
-1.050 -1.145 -1.085 -1.037 -1.416 -1.145 -1.085 -1.037 -1.416
-1.291 -1.406 -1.533 -1.471 -1.865 -1.406 -1.533 -1.471 -1.865
-1.040 -1.134 -1.069 -1.021 -1.400 -1.134 -1.069 -1.021 -1.400
-1.281 -1.395 -1.517 -1.455 -1.849 -1.395 -1.517 -1.455 -1.849
-1.040 -1.134 -1.069 -1.021 -1.400 -1.134 -1.069 -1.021 -1.400
-1.281 -1.395 -1.517 -1.455 -1.849 -1.395 -1.517 -1.455 -1.849
-1.153 -1.263 -1.311 -1.265 -1.644 -1.263 -1.311 -1.265 -1.644
-1.394 -1.524 -1.762 -1.702 -2.093 -1.524 -1.762 -1.702 -2.093
1.222
1.659
1.212
1.649
1.212
1.649
1.326
1.763
1.1 V
V
-1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763
-1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763
-1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763
-1.182 -1.297 -1.516 -1.463 -1.735 -1.305 -1.518 -1.469 -1.768
-1.182 -1.297 -1.516 -1.463 -1.735 -1.305 -1.518 -1.469 -1.768
1.582
1.371
1.582
1.371
1.368
1.585
1.368
C2
CCL
1.1 V
V
C2
CCL
=
=
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1.338
1.818
1.327
1.807
1.327
1.807
1.459
1.939
1.1 V
V
1.801
1.505
1.801
1.505
1.506
1.800
1.506
C3
1.1 V
CCL
V
C3
CCL
=
=
1.303
1.989
1.287
1.973
1.287
1.973
1.532
2.221
1.1 V
V
1.915
1.747
1.915
1.747
1.750
1.912
1.750
C4
CCL
1.1 V
V
C4
CCL
=
=
1.245
1.905
1.229
1.889
1.229
1.889
1.474
2.137
1.1 V
V
1.799
1.679
1.799
1.679
1.682
1.796
1.682
1.1 V
CCL
V
CCL
=
=
C4L
C4L
1.616
2.306
1.600
2.290
1.600
2.290
1.849
2.539
0.9 V
V
1.814
1.951
1.814
1.951
1.954
1.811
1.954
0.9 V
V
CCL
CCL
=
=
© July 2010 Altera Corporation
1.338
1.818
1.327
1.807
1.327
1.807
1.459
1.939
1.1 V
V
1.796
1.526
1.796
1.526
1.525
1.797
1.525
1.1 V
I3
V
CCL
I3
CCL
=
=
1.303
1.989
1.287
1.973
1.287
1.973
1.532
2.221
1.1 V
V
1.923
1.756
1.923
1.756
1.761
1.918
1.761
1.1 V
I4
V
CCL
CCL
I4
=
=
I/O Timing
1.245
1.905
1.229
1.889
1.229
1.889
1.474
2.137
1.1 V
V
1.804
1.693
1.804
1.693
1.698
1.799
1.698
1.1 V
V
CCL
CCL
=
=
I4L
I4L
1.616
2.306
1.600
2.290
1.600
2.290
1.849
2.539
0.9 V
V
1.865
1.982
1.865
1.982
1.987
1.860
1.987
0.9 V
V
CCL
CCL
=
=
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns