DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 275

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–126. EP3SE110 Row Pins Input Timing Parameters (Part 3 of 3)
Table 1–127. EP3SE110 Column Pins Output Timing Parameters (Part 1 of 4)
© July 2010 Altera Corporation
DIFFERENTIAL
2.5-V
SSTL CLASS II
LVDS_E_1R
LVDS_E_3R
MINI-
LVDS_E_1R
MINI-
LVDS_E_3R
RSDS_E_1R
RSDS_E_3R
I/O Standard
I/O Standard
—
—
—
—
—
—
GCLK
GCLK
Clock
PLL
Table 1–127
I/O standards.
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
PLL
PLL
PLL
t
t
t
t
su
su
h
h
Industrial
-0.781
-0.861
0.907
1.124
t
t
t
t
t
t
t
t
t
t
t
t
co
co
co
co
co
co
co
co
co
co
co
co
lists the EP3SE110 column pins output timing parameters for differential
Fast Model
Industrial
3.152
1.328
3.148
1.324
3.152
1.328
3.148
1.324
3.152
1.328
3.148
1.324
Commercial
Fast Model
-0.827
-0.861
0.969
1.141
Commercial
3.387
1.502
3.390
1.505
3.387
1.502
3.390
1.505
3.387
1.502
3.390
1.505
-1.178 -1.275 -1.384 -1.333 -1.673 -1.273 -1.378 -1.329 -1.712
-1.411 -1.601 -1.780 -1.688 -1.617 -1.610 -1.792 -1.699 -1.665
1.379
1.827
1.1 V
V
C2
CCL
=
4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899
1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237
4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965
1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303
4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899
1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237
4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965
1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303
4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899
1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237
4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965
1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303
V
1.1V
C2
CCL
1.502
2.068
1.1 V
V
C3
CCL
=
=
V
1.1V
C3
CCL
1.631
2.299
1.1 V
V
=
C4
CCL
=
V
1.1V
C4
CCL
1.568
2.178
1.1 V
=
V
CCL
=
V
1.1V
C4L
CCL
=
1.912
2.118
0.9 V
V
Stratix III Device Handbook, Volume 2
C4L
CCL
=
V
0.9V
CCL
=
1.509
2.089
1.1 V
V
I3
CCL
V
1.1V
=
I3
CCL
=
1.636
2.323
1.1 V
V
I4
CCL
V
1.1V
=
I4
CCL
=
1.573
2.199
1.1 V
V
1–275
CCL
V
1.1V
CCL
=
=
I4L
I4L
1.952
2.170
0.9 V
V
V
0.9V
CCL
CCL
=
=
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns