DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 240

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–240
Table 1–113. EP3SE80 Column Pins Output Timing Parameters (Part 7 of 7)
Table 1–114. EP3SE80 Row Pins Output Timing Parameters (Part 1 of 5)
Stratix III Device Handbook, Volume 2
1.2-V
HSTL
CLASS I
1.2-V
HSTL
CLASS II
3.0-V PCI
3.0-V
PCI-X
3.3-V
LVTTL
Standard
Standard
I/O
I/O
4mA
8mA
12mA
4mA
6mA
8mA
10mA
12mA
16mA
—
—
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Table 1–114
standards.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
Industrial
Industrial
3.238
1.439
3.156
1.346
3.077
1.247
3.312
3.706
3.298
3.698
3.292
3.699
3.277
3.688
3.277
3.688
3.327
3.709
3.395
3.812
3.395
3.812
lists the EP3SE80 row pins output timing parameters for single-ended I/O
Fast Model
Fast Model
Commercial
Commercial
3.493
1.634
3.399
1.529
3.310
1.423
3.312
3.712
3.298
3.704
3.292
3.705
3.277
3.694
3.277
3.694
3.327
3.715
3.395
3.818
3.395
3.818
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
4.856 5.245 5.757 5.609 5.907 5.368 5.891 5.735 5.990
2.039 2.121 2.343 2.334 2.309 2.226 2.430 2.441 2.301
4.726 5.107 5.612 5.464 5.762 5.227 5.742 5.586 5.841
1.909 1.983 2.198 2.189 2.195 2.085 2.281 2.292 2.186
4.607 4.984 5.484 5.348 5.634 5.107 5.610 5.468 5.709
1.790 1.860 2.070 2.061 2.099 1.958 2.149 2.160 2.086
4.688 5.081 5.529 5.499 5.756 5.081 5.529 5.499 5.756
5.267 5.709 6.287 6.101 6.522 5.709 6.287 6.101 6.522
4.674 5.066 5.520 5.482 5.747 5.066 5.520 5.482 5.747
5.258 5.700 6.278 6.092 6.513 5.700 6.278 6.092 6.513
4.675 5.068 5.529 5.478 5.756 5.068 5.529 5.478 5.756
5.266 5.708 6.287 6.101 6.522 5.708 6.287 6.101 6.522
4.657 5.049 5.515 5.455 5.742 5.049 5.515 5.455 5.742
5.253 5.695 6.273 6.087 6.508 5.695 6.273 6.087 6.508
4.657 5.049 5.516 5.456 5.743 5.049 5.516 5.456 5.743
5.253 5.695 6.274 6.088 6.509 5.695 6.274 6.088 6.509
4.692 5.083 5.529 5.534 5.756 5.083 5.529 5.534 5.756
5.269 5.710 6.287 6.101 6.522 5.710 6.287 6.101 6.522
4.701 5.080 5.554 5.509 5.781 5.080 5.554 5.509 5.781
5.314 5.744 6.312 6.126 6.547 5.744 6.312 6.126 6.547
4.701 5.080 5.554 5.509 5.781 5.080 5.554 5.509 5.781
5.314 5.744 6.312 6.126 6.547 5.744 6.312 6.126 6.547
1.1 V
V
1.1 V
V
C2
CCL
C2
CCL
=
=
1.1 V
V
1.1 V
V
C3
CCL
C3
CCL
=
=
1.1 V
V
1.1 V
V
C4
CCL
C4
CCL
=
=
1.1 V
V
1.1 V
V
CCL
CCL
=
=
C4L
C4L
0.9 V
V
0.9 V
V
CCL
CCL
© July 2010 Altera Corporation
=
=
1.1 V
V
1.1 V
V
CCL
I3
I3
CCL
=
=
1.1 V
V
1.1 V
V
I4
CCL
I4
CCL
=
=
I/O Timing
1.1 V
V
1.1 V
V
CCL
CCL
=
=
I4L
I4L
0.9 V
0.9 V
V
V
CCL
CCL
=
=
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns