DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 313
DK-DEV-3SL150N
Manufacturer Part Number
DK-DEV-3SL150N
Description
KIT DEVELOPMENT STRATIX III
Manufacturer
Altera
Series
Stratix® IIIr
Type
FPGAr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.DK-DEV-3SL150N.pdf
(34 pages)
Specifications of DK-DEV-3SL150N
Contents
Development Platform, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP3S
Silicon Family Name
Stratix III
Kit Contents
Development Board, Cable And Accessories
Rohs Compliant
Yes
For Use With/related Products
EP3SL150F152
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2568
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-3SL150N
Manufacturer:
Altera
Quantity:
135
- Current page: 313 of 332
- Download datasheet (4Mb)
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–152. EP3SL70 Column Pin Periphery Clock Timing Specifications
Table 1–153. EP3SL70 Row Pin Periphery Clock Timing Specifications
.
Table 1–154. EP3SL110 Column Pin Global Clock Timing Specifications
Table 1–155. EP3SL110 Row Pin Global Clock Timing Specifications
© July 2010 Altera Corporation
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Parameter
Parameter
Parameter
Parameter
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
Industrial
Industrial
Industrial
Industrial
-0.068
-0.068
-0.019
-0.101
-0.048
-0.048
-0.002
-0.084
1.465
1.465
1.482
1.400
1.909
1.909
1.882
1.800
Fast Model
Fast Model
Fast Model
Fast Model
Table 1–152
devices.
EP3SL110 Clock Timing Parameters
Table 1–154
devices.
Commercial
Commercial
Commercial
Commercial
-0.083
-0.083
-0.052
-0.050
-0.050
-0.032
1.468
1.468
1.558
1.467
0.039
1.907
1.907
2.014
1.923
0.059
and
and
Table 1–153
Table 1–155
-0.330 -0.370 -0.334
-0.330 -0.370 -0.334
-0.225 -0.302 -0.291
-0.367 -0.465 -0.472
-0.274 -0.330 -0.290
-0.274 -0.330 -0.290
-0.202 -0.271 -0.231
-0.347 -0.434 -0.412
2.142
2.142
2.227
2.082
2.674
2.674
2.754
2.612
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C2
C2
C2
C2
CCL
CCL
CCL
CCL
=
=
=
=
2.410
2.410
2.488
2.325
2.936
2.936
2.975
2.812
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C3
C3
C3
C3
CCL
CCL
CCL
CCL
list the periphery clock timing parameters for EP3SL70
list the global clock timing parameters for EP3SL110
=
=
=
=
2.792
2.792
2.851
2.670
3.285
3.285
3.344
3.163
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C4
C4
C4
C4
CCL
CCL
CCL
CCL
=
=
=
=
-0.288
-0.288
-0.235
-0.406
-0.251
-0.251
-0.184
-0.355
2.673
2.673
2.727
2.556
3.182
3.182
3.221
3.050
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
C4L
C4L
C4L
C4L
-0.133
-0.133
-0.295
-0.454
-0.032
-0.032
-0.212
-0.371
3.220
3.220
3.031
2.872
3.700
3.700
3.511
3.352
0.9 V
0.9 V
0.9 V
0.9 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
-0.370
-0.370
-0.261
-0.431
-0.330
-0.330
-0.219
-0.389
2.410
2.410
2.539
2.369
2.936
2.936
3.062
2.892
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
I3
CCL
I3
CCL
I3
CCL
I3
CCL
Stratix III Device Handbook, Volume 2
=
=
=
=
-0.290
-0.290
-0.184
-0.373
2.802
2.802
0.273
0.273
2.905
2.716
0.376
0.187
3.285
3.285
3.413
3.224
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
I4
CCL
I4
CCL
I4
CCL
I4
CCL
=
=
=
=
-0.288 -0.133
-0.288 -0.133
-0.188 -0.257
-0.367 -0.416
-0.251 -0.032
-0.251 -0.032
-0.138 -0.260
-0.317 -0.419
2.673
2.673
2.777
2.598
3.182
3.182
3.287
3.108
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
I4L
I4L
I4L
I4L
3.220
3.220
3.056
2.897
3.700
3.700
3.551
3.392
0.9 V
0.9 V
0.9 V
0.9 V
V
V
V
V
1–313
CCL
CCL
CCL
CCL
=
=
=
=
Units
Units
Units
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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