DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 13

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Switching Characteristics
Switching Characteristics
Core Performance Specifications
© July 2010 Altera Corporation
This section provides performance characteristics of Stratix III core and periphery
blocks for commercial grade devices.
These characteristics can be designated as Preliminary and Final and each
designation is defined below.
Preliminary—Preliminary characteristics are created using simulation results, process
data, and other known parameters.
Final—Final numbers are based on actual silicon characterization and testing. These
numbers reflect the actual performance of the device under worst-case silicon process,
voltage, and junction temperature conditions. The upper-right hand corner of a table
shows the designation as Preliminary or Final.
These sections describe the Clock Tree, PLL, digital signal processing (DSP),
TriMatrix, and Configuration and JTAG specifications.
Clock Tree Specifications
Table 1–19
blocks, and TriMatrix Memory blocks for Stratix III devices.
Table 1–19. Clock Tree Performance for Stratix III Devices
PLL Specifications
Table 1–20
commercial junction temperature range (0 to 85° C) and the industrial junction
temperature range (-40 to 100° C), except for EP3SL340, EP3SE260, and EP3SL200
devices in the I4L ordering code, where the industrial junction temperature range is
from 0° C to 100° C, regardless of supply voltage. Refer to the figure in “PLL
Specifications” in
EP3SL50
EP3SL70
EP3SL110
EP3SL150
EP3SL200
EP3SE260
EP3SL340
EP3SE50
EP3SE80
EP3SE110
Device
lists the clock tree performance specifications for the logic array, DSP
lists the Stratix III PLL specifications when operating in both the
V
CCL
730
730
730
730
730
730
730
730
730
730
= 1.1 V
C2
“Glossary” on page 1–326
V
CCL
C3, I3
700
700
700
700
700
700
700
700
700
700
= 1.1 V
V
CCL
C4, I4
450
450
450
450
450
450
450
450
450
450
= 1.1 V
for the PLL block diagram.
V
CCL
450
450
450
450
450
450
450
450
450
450
= 1.1 V
Stratix III Device Handbook, Volume 2
C4L, I4L
V
CCL
375
375
375
375
375
375
375
375
375
375
= 0.9 V
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
1–13