DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 317

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–168. EP3SL200 Column Pin Regional Clock Timing Specifications
Table 1–169. EP3SL200 Row Pin Regional Clock Timing Specifications
Table 1–170. EP3SL200 Column Pin Periphery Clock Timing Specifications
Table 1–171. EP3SL200 Row Pin Periphery Clock Timing Specifications
© July 2010 Altera Corporation
t
t
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t
t
t
t
t
t
t
t
t
t
t
t
t
Parameter
Parameter
Parameter
Parameter
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
Industrial
Industrial
Industrial
Industrial
2.006
2.006
0.059
0.059
1.937
1.855
0.126
0.044
1.720
1.720
0.037
0.037
1.501
1.419
0.105
0.023
Fast Model
Fast Model
Fast Model
Fast Model
Table 1–168
Table 1–170
devices.
Commercial
Commercial
Commercial
Commercial
2.035
2.035
0.086
0.086
2.065
1.974
0.197
0.106
1.712
1.712
0.064
0.064
1.575
1.484
0.174
0.083
and
and
Table 1–169
Table 1–171
-0.150 -0.191 -0.109
-0.150 -0.191 -0.109
-0.059 -0.091 -0.051
-0.211 -0.254 -0.232
-0.173 -0.213 -0.135
-0.173 -0.213 -0.135
-0.081 -0.118 -0.077
-0.233 -0.281 -0.258
3.020
3.020
3.000
2.848
2.615
2.615
2.380
2.225
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C2
C2
C2
C2
CCL
CCL
CCL
CCL
=
=
=
=
3.113
3.113
3.070
2.910
2.776
2.776
2.518
2.355
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C3
C3
C3
C3
CCL
CCL
CCL
CCL
list the regional clock timing parameters for EP3SL200.
list the periphery clock timing parameters for EP3SL200
=
=
=
=
3.494
3.494
3.414
3.233
3.177
3.177
2.892
2.711
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C4
C4
C4
C4
CCL
CCL
CCL
CCL
=
=
=
=
-0.094
-0.094
-0.036
-0.207
-0.118
-0.118
-0.061
-0.232
3.213
3.213
3.275
3.104
3.044
3.044
2.761
2.590
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
C4L
C4L
C4L
C4L
-0.041
-0.200
-0.063
-0.222
3.743
3.743
3.597
3.438
3.660
3.660
3.077
2.918
0.116
0.116
0.090
0.090
0.9 V
0.9 V
0.9 V
0.9 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
-0.191
-0.191
-0.043
-0.213
-0.213
-0.213
-0.067
-0.237
3.113
3.113
3.139
2.971
2.776
2.776
2.567
2.397
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
I3
CCL
I3
CCL
I3
CCL
I3
CCL
Stratix III Device Handbook, Volume 2
=
=
=
=
3.531
3.531
0.291
0.291
3.479
3.290
0.410
0.221
3.177
3.177
0.292
0.292
2.938
2.749
0.411
0.222
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
I4
CCL
I4
CCL
I4
CCL
I4
CCL
=
=
=
=
-0.094
-0.094
-0.036 -0.041
-0.207 -0.200
-0.118
-0.118
-0.061 -0.063
-0.232 -0.222
3.213
3.213
3.275
3.104
3.044
3.044
2.761
2.590
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
I4L
I4L
I4L
I4L
3.743
3.743
0.116
0.116
3.597
3.438
3.660
3.660
0.090
0.090
3.077
2.918
0.9 V
0.9 V
0.9 V
0.9 V
V
V
V
V
1–317
CCL
CCL
CCL
CCL
=
=
=
=
Units
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns