DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 179

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–92. EP3SL340 Row Pins Input Timing Parameters (Part 3 of 3)
© July 2010 Altera Corporation
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS II
1.2-V HSTL
CLASS I
1.2-V HSTL
CLASS II
3.0-V PCI
3.0-V
PCI-X
Standard
I/O
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
PLL
PLL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
h
h
h
h
Industrial
-1.141
-0.672
-1.141
-0.672
-1.132
-0.681
-1.132
-0.681
-1.245
-0.609
-1.245
-0.609
1.267
0.937
1.267
0.937
1.258
0.946
1.258
0.946
1.368
0.873
1.368
0.873
Fast Model
Commercial
-1.232
-0.735
-1.232
-0.735
-1.220
-0.747
-1.220
-0.747
-1.307
-0.649
-1.307
-0.649
1.371
1.021
1.371
1.021
1.359
1.033
1.359
1.033
1.446
0.934
1.446
0.934
-1.824 -1.825 -1.954 -1.887 -2.333 -1.833 -1.964 -1.908 -2.377
-1.323 -1.336 -1.580 -1.496 -1.313 -1.312 -1.591 -1.499 -1.355
-1.824 -1.825 -1.954 -1.887 -2.333 -1.833 -1.964 -1.908 -2.377
-1.323 -1.336 -1.580 -1.496 -1.313 -1.312 -1.591 -1.499 -1.355
-1.815 -1.815 -1.938 -1.871 -2.317 -1.824 -1.948 -1.892 -2.361
-1.332 -1.346 -1.596 -1.512 -1.329 -1.321 -1.607 -1.515 -1.371
-1.815 -1.815 -1.938 -1.871 -2.317 -1.824 -1.948 -1.892 -2.361
-1.332 -1.346 -1.596 -1.512 -1.329 -1.321 -1.607 -1.515 -1.371
-1.922 -1.957 -2.202 -2.138 -2.590 -1.972 -2.209 -2.147 -2.527
-1.219 -1.216 -1.260 -1.185 -1.175 -1.209 -1.268 -1.188 -1.226
-1.922 -1.957 -2.202 -2.138 -2.590 -1.972 -2.209 -2.147 -2.527
-1.219 -1.216 -1.260 -1.185 -1.175 -1.209 -1.268 -1.188 -1.226
2.038
1.778
2.038
1.778
2.029
1.787
2.029
1.787
2.134
1.673
2.134
1.673
1.1 V
V
C2
CCL
=
2.044
1.804
2.044
1.804
2.034
1.814
2.034
1.814
2.178
1.686
2.178
1.686
1.1 V
V
C3
CCL
=
2.195
2.104
2.195
2.104
2.179
2.120
2.179
2.120
2.445
1.783
2.445
1.783
1.1 V
V
C4
CCL
=
2.117
1.990
2.117
1.990
2.101
2.006
2.101
2.006
2.369
1.677
2.369
1.677
1.1 V
V
CCL
=
C4L
2.564
1.814
2.564
1.814
2.548
1.830
2.548
1.830
2.825
1.686
2.825
1.686
0.9 V
Stratix III Device Handbook, Volume 2
V
CCL
=
2.062
1.790
2.062
1.790
2.053
1.799
2.053
1.799
2.204
1.690
2.204
1.690
1.1 V
V
I3
CCL
=
2.214
2.127
2.214
2.127
2.198
2.143
2.198
2.143
2.461
1.802
2.461
1.802
1.1 V
V
CCL
I4
=
2.147
2.005
2.147
2.005
2.131
2.021
2.131
2.021
2.387
1.690
2.387
1.690
1.1 V
1–179
V
CCL
=
I4L
2.611
1.863
2.611
1.863
2.595
1.879
2.595
1.879
2.768
1.741
2.768
1.741
0.9 V
V
CCL
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns