DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 258

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–258
Table 1–121. EP3SE110 Column Pins Input Timing Parameters (Part 4 of 4)
Table 1–122. EP3SE110 Row Pins Input Timing Parameters (Part 1 of 3)
Stratix III Device Handbook, Volume 2
3.0-V
PCI-X
3.3-V
LVTTL
3.3-V
LVCMOS
3.0-V
LVTTL
3.0-V
LVCMOS
2.5 V
1.8 V
Standard
Standard
I/O
I/O
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
PLL
PLL
PLL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
su
su
su
su
t
t
Table 1–122
standards.
h
h
h
h
h
h
h
h
h
h
h
h
t
t
su
su
h
h
Industrial
Industrial
-0.917
-0.762
-0.917
-0.762
-0.923
-0.756
-0.923
-0.756
-0.911
-0.768
-0.987
-0.777
1.041
1.022
1.041
1.022
1.047
1.016
1.047
1.016
1.035
1.028
1.112
1.040
-1.041
-1.308
1.183
1.611
Fast Model
Fast Model
lists the EP3SE110 row pins input timing parameters for single-ended I/O
Commercial
Commercial
-0.960
-0.722
-0.960
-0.722
-0.971
-0.711
-0.971
-0.711
-0.964
-0.718
-1.042
-0.773
1.099
1.000
1.099
1.000
1.110
0.989
1.110
0.989
1.103
0.996
1.182
1.054
-1.017
-1.278
1.155
1.576
-1.364 -1.476 -1.736 -1.642 -2.026 -1.488 -1.737 -1.683 -2.064
-1.218 -1.386 -1.449 -1.406 -1.309 -1.426 -1.456 -1.368 -1.357
-1.364 -1.476 -1.736 -1.642 -2.026 -1.488 -1.737 -1.683 -2.064
-1.218 -1.386 -1.449 -1.406 -1.309 -1.426 -1.456 -1.368 -1.357
-1.361 -1.477 -1.739 -1.645 -2.029 -1.487 -1.742 -1.688 -2.069
-1.221 -1.385 -1.446 -1.403 -1.306 -1.427 -1.451 -1.363 -1.352
-1.361 -1.477 -1.739 -1.645 -2.029 -1.487 -1.742 -1.688 -2.069
-1.221 -1.385 -1.446 -1.403 -1.306 -1.427 -1.451 -1.363 -1.352
-1.370 -1.490 -1.754 -1.660 -2.044 -1.496 -1.752 -1.698 -2.079
-1.212 -1.372 -1.431 -1.388 -1.291 -1.418 -1.441 -1.353 -1.342
-1.456 -1.570 -1.756 -1.705 -2.042 -1.576 -1.754 -1.707 -2.080
-1.286 -1.461 -1.433 -1.472 -1.399 -1.468 -1.440 -1.352 -1.447
1.561
1.632
1.561
1.632
1.558
1.635
1.558
1.635
1.567
1.626
1.653
1.703
1.1 V
V
C2
CCL
-1.453 -1.615 -1.846 -1.785 -2.147 -1.615 -1.846 -1.785 -2.147
-1.830 -2.025 -2.260 -2.186 -2.654 -2.025 -2.260 -2.186 -2.654
1.647
2.261
1.1 V
V
=
C2
CCL
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
=
1.698
1.851
1.698
1.851
1.699
1.850
1.699
1.850
1.712
1.837
1.793
1.929
1.1 V
V
C3
CCL
1.840
2.516
1.1 V
V
=
C3
CCL
=
1.978
1.964
1.978
1.964
1.981
1.961
1.981
1.961
1.996
1.946
1.999
1.948
1.1 V
V
C4
CCL
2.092
2.792
1.1 V
V
=
C4
CCL
=
1.873
1.893
1.873
1.893
1.876
1.890
1.876
1.890
1.891
1.875
1.936
1.963
1.1 V
V
CCL
2.016
2.688
1.1 V
=
V
C4L
CCL
=
2.261
1.808
2.261
1.808
2.264
1.805
2.264
1.805
2.279
1.790
2.277
1.900
0.9 V
C4L
V
CCL
2.384
3.179
=
0.9 V
V
CCL
© July 2010 Altera Corporation
=
1.720
1.901
1.720
1.901
1.719
1.902
1.719
1.902
1.728
1.893
1.808
1.946
1.1 V
V
I3
CCL
=
1.840
2.516
1.1 V
V
I3
CCL
=
1.989
1.982
1.989
1.982
1.994
1.977
1.994
1.977
2.004
1.967
2.007
1.966
1.1 V
V
CCL
I4
=
2.092
2.792
1.1 V
V
CCL
I4
=
I/O Timing
1.922
1.864
1.922
1.864
1.927
1.859
1.927
1.859
1.937
1.849
1.948
1.848
1.1 V
V
CCL
=
2.016
2.688
1.1 V
V
I4L
CCL
=
2.300
1.859
2.300
1.859
2.305
1.854
2.305
1.854
2.315
1.844
2.316
1.952
0.9 V
V
I4L
CCL
=
2.384
3.179
0.9 V
V
CCL
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns