DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 260

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–260
Table 1–122. EP3SE110 Row Pins Input Timing Parameters (Part 3 of 3)
Stratix III Device Handbook, Volume 2
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS II
1.2-V HSTL
CLASS I
1.2-V HSTL
CLASS II
3.0-V PCI
3.0-V
PCI-X
Standard
I/O
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
PLL
PLL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
h
h
h
h
Industrial
-0.877
-0.887
-0.877
-0.887
-0.868
-0.896
-0.868
-0.896
-0.923
-0.756
-0.923
-0.756
1.002
1.150
1.002
1.150
0.993
1.159
0.993
1.159
1.047
1.016
1.047
1.016
Fast Model
Commercial
-0.931
-0.884
-0.931
-0.884
-0.919
-0.896
-0.919
-0.896
-0.971
-0.711
-0.971
-0.711
1.071
1.165
1.071
1.165
1.059
1.177
1.059
1.177
1.110
0.989
1.110
0.989
-1.300 -1.400 -1.506 -1.454 -1.793 -1.406 -1.513 -1.462 -1.836
-1.439 -1.631 -1.685 -1.722 -1.650 -1.638 -1.687 -1.598 -1.693
-1.300 -1.400 -1.506 -1.454 -1.793 -1.406 -1.513 -1.462 -1.836
-1.439 -1.631 -1.685 -1.722 -1.650 -1.638 -1.687 -1.598 -1.693
-1.291 -1.390 -1.490 -1.438 -1.777 -1.397 -1.497 -1.446 -1.820
-1.448 -1.641 -1.701 -1.738 -1.666 -1.647 -1.703 -1.614 -1.709
-1.291 -1.390 -1.490 -1.438 -1.777 -1.397 -1.497 -1.446 -1.820
-1.448 -1.641 -1.701 -1.738 -1.666 -1.647 -1.703 -1.614 -1.709
-1.361 -1.477 -1.739 -1.645 -2.029 -1.487 -1.742 -1.688 -2.069
-1.221 -1.385 -1.446 -1.403 -1.306 -1.427 -1.451 -1.363 -1.352
-1.361 -1.477 -1.739 -1.645 -2.029 -1.487 -1.742 -1.688 -2.069
-1.221 -1.385 -1.446 -1.403 -1.306 -1.427 -1.451 -1.363 -1.352
1.498
1.857
1.498
1.857
1.489
1.866
1.489
1.866
1.558
1.635
1.558
1.635
1.1 V
V
C2
CCL
=
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1.621
2.097
1.621
2.097
1.611
2.107
1.611
2.107
1.699
1.850
1.699
1.850
1.1 V
V
C3
CCL
=
1.747
2.198
1.747
2.198
1.731
2.214
1.731
2.214
1.981
1.961
1.981
1.961
1.1 V
V
C4
CCL
=
1.684
2.211
1.684
2.211
1.668
2.227
1.668
2.227
1.876
1.890
1.876
1.890
1.1 V
V
CCL
=
C4L
2.024
2.147
2.024
2.147
2.008
2.163
2.008
2.163
2.264
1.805
2.264
1.805
0.9 V
V
CCL
=
© July 2010 Altera Corporation
1.636
2.113
1.636
2.113
1.627
2.122
1.627
2.122
1.719
1.902
1.719
1.902
1.1 V
V
I3
CCL
=
1.761
2.210
1.761
2.210
1.745
2.226
1.745
2.226
1.994
1.977
1.994
1.977
1.1 V
V
I4
CCL
=
I/O Timing
1.702
2.093
1.702
2.093
1.686
2.109
1.686
2.109
1.927
1.859
1.927
1.859
1.1 V
V
CCL
=
I4L
2.068
2.194
2.068
2.194
2.052
2.210
2.052
2.210
2.305
1.854
2.305
1.854
0.9 V
V
CCL
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns