DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 93

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–60. EP3SL70 Row Pin Delay Adders for Regional Clock
Table 1–61. EP3SL110 Column Pins Input Timing Parameters (Part 1 of 3)
© July 2010 Altera Corporation
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
3.3-V LVTTL
3.3-V
LVCMOS
3.0-V LVTTL
3.0-V
LVCMOS
2.5 V
Standard
I/O
Parameter
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
PLL
Table 1–60
EP3SL110 I/O Timing Parameters
Table 1–61
devices for single-ended I/O standards.
Table 1–61
I/O standards.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
h
h
Industrial
-0.113
-0.107
Industrial
0.111
0.099
-0.917
-1.234
-0.917
-1.234
-0.928
-1.245
-0.928
-1.245
-0.923
-1.240
1.053
1.512
1.053
1.512
1.064
1.523
1.064
1.523
1.059
1.518
Fast Model
Fast Model
through
lists the EP3SL70 row pin delay adders when using the regional clock.
lists the EP3SL110 column pins input timing parameters for single-ended
Commercial
Commercial
-0.127
-0.112
0.123
0.105
-0.917
-1.176
-0.917
-1.176
-0.928
-1.187
-0.928
-1.187
-0.923
-1.182
1.053
1.460
1.053
1.460
1.064
1.471
1.064
1.471
1.059
1.466
Table 1–65
-0.183 -0.198 -0.213 -0.205 -0.272 -0.202 -0.216
-0.164 -0.185 -0.202 -0.193 -0.258 -0.184 -0.204 -0.197 -0.257
-1.333 -1.452 -1.682 -1.627 -1.980 -1.452 -1.682 -1.627 -1.980
-1.704 -1.940 -2.210 -2.135 -2.470 -1.940 -2.210 -2.135 -2.470
-1.333 -1.452 -1.682 -1.627 -1.980 -1.452 -1.682 -1.627 -1.980
-1.704 -1.940 -2.210 -2.135 -2.470 -1.940 -2.210 -2.135 -2.470
-1.332 -1.454 -1.681 -1.626 -1.979 -1.454 -1.681 -1.626 -1.979
-1.703 -1.942 -2.209 -2.134 -2.469 -1.942 -2.209 -2.134 -2.469
-1.332 -1.454 -1.681 -1.626 -1.979 -1.454 -1.681 -1.626 -1.979
-1.703 -1.942 -2.209 -2.134 -2.469 -1.942 -2.209 -2.134 -2.469
-1.341 -1.466 -1.700 -1.645 -1.998 -1.466 -1.700 -1.645 -1.998
-1.712 -1.954 -2.228 -2.153 -2.488 -1.954 -2.228 -2.153 -2.488
1.1 V
0.177
0.156
1.524
2.116
1.524
2.116
1.523
2.115
1.523
2.115
1.532
2.124
V
1.1 V
V
C2
CCL
C2
CCL
=
=
list the maximum I/O timing parameters for EP3SL110
1.667
2.394
1.667
2.394
1.669
2.396
1.669
2.396
1.681
2.408
0.192
0.175
1.1 V
1.1 V
V
V
C3
C3
CCL
CCL
=
=
1.918
2.710
1.918
2.710
1.917
2.709
1.917
2.709
1.936
2.728
0.207
0.195
1.1 V
V
1.1 V
V
C4
C4
CCL
CCL
=
=
1.850
2.610
1.850
2.610
1.849
2.609
1.849
2.609
1.868
2.628
0.198
0.185
1.1 V
V
1.1 V
V
CCL
CCL
=
=
C4L
C4L
2.205
2.971
2.205
2.971
2.204
2.970
2.204
2.970
2.223
2.989
0.263
0.263
0.9 V
V
0.9 V
V
CCL
CCL
Stratix III Device Handbook, Volume 2
=
=
1.667
2.394
1.667
2.394
1.669
2.396
1.669
2.396
1.681
2.408
1.1 V
0.194
0.177
V
1.1 V
V
I3
CCL
CCL
I3
=
=
1.918
2.710
1.918
2.710
1.917
2.709
1.917
2.709
1.936
2.728
0.212
1.1 V
0.195
V
1.1 V
V
I4
CCL
I4
CCL
=
=
1.850
2.610
1.850
2.610
1.849
2.609
1.849
2.609
1.868
2.628
1.1 V
0.201
0.188
-0.21
V
1.1 V
V
CCL
CCL
=
1–93
=
I4L
I4L
2.205
2.971
2.205
2.971
2.204
2.970
2.204
2.970
2.223
2.989
-0.273
0.9 V
0.266
0.263
V
0.9 V
V
CCL
CCL
=
=
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns