DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 271

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–124. EP3SE110 Row Pins Output Timing Parameters (Part 5 of 5)
Table 1–125. EP3SE110 Column Pins Input Timing Parameters (Part 1 of 3)
© July 2010 Altera Corporation
1.2-V
HSTL
CLASS I
3.0-V PCI
3.0-V
PCI-X
LVDS
MINI-LVDS
RSDS
DIFFERENTIAL
1.2-V HSTL
CLASS I
Standard
I/O Standard
I/O
4mA
6mA
8mA
—
—
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
PLL
PLL
Table 1–125
EP3SE110 devices for differential I/O standards.
Table 1–125
I/O standards.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
t
t
t
t
t
t
t
t
t
t
co
co
co
co
co
co
co
co
co
co
Industrial Commercial
-0.997
-0.691
-0.997
-0.691
-0.997
-0.691
-0.813
-0.882
1.133
0.960
1.133
0.960
1.133
0.960
0.942
1.144
Industrial
3.053
1.255
3.044
1.243
3.043
1.241
3.163
1.354
3.163
1.354
Fast Model
through
lists the EP3SE110 column pins input timing parameters for differential
Fast Model
-1.029
-0.701
-1.029
-0.701
-1.029
-0.701
-0.852
-0.886
1.184
0.994
1.184
0.994
1.184
0.994
0.999
1.171
Commercial
Table 1–128
3.287
1.430
3.279
1.418
3.279
1.416
3.401
1.570
3.401
1.570
-1.181 -1.169 -1.324 -1.269 -1.645 -1.133 -1.542 -1.230 -1.683
-1.428 -1.714 -1.834 -1.749 -1.648 -1.756 -1.968 -1.795 -1.697
-1.181 -1.169 -1.324 -1.269 -1.645 -1.133 -1.542 -1.230 -1.683
-1.428 -1.714 -1.834 -1.749 -1.648 -1.756 -1.968 -1.795 -1.697
-1.181 -1.169 -1.324 -1.269 -1.645 -1.133 -1.542 -1.230 -1.683
-1.428 -1.714 -1.834 -1.749 -1.648 -1.756 -1.968 -1.795 -1.697
-1.258 -1.368 -1.483 -1.423 -1.794 -1.368 -1.482 -1.428 -1.837
-1.383 -1.555 -1.721 -1.641 -1.544 -1.563 -1.729 -1.645 -1.588
1.415
1.879
1.415
1.879
1.415
1.879
1.460
1.802
1.1 V
V
C2
CCL
=
4.661 5.057 5.585 5.428 5.728 5.174 5.705 5.574 5.805
1.847 1.936 2.137 2.157 2.162 2.035 2.239 2.258 2.150
4.650 5.045 5.576 5.416 5.719 5.163 5.696 5.565 5.796
1.836 1.924 2.125 2.145 2.150 2.024 2.228 2.247 2.139
4.654 5.050 5.585 5.422 5.728 5.169 5.706 5.575 5.806
1.840 1.929 2.131 2.151 2.156 2.030 2.235 2.254 2.146
4.709 5.091 5.611 5.451 5.758 5.213 5.734 5.603 5.837
1.920 1.997 2.156 2.167 2.156 2.061 2.263 2.282 2.149
4.709 5.091 5.611 5.451 5.758 5.213 5.734 5.603 5.837
1.920 1.997 2.156 2.167 2.156 2.061 2.263 2.282 2.149
1.1 V
V
C2
list the maximum I/O timing parameters for
CCL
=
1.436
2.224
1.436
2.224
1.436
2.224
1.595
2.025
1.1 V
V
C3
CCL
=
1.1 V
V
C3
CCL
=
1.618
2.401
1.618
2.401
1.618
2.401
1.731
2.242
1.1 V
V
C4
CCL
1.1 V
V
=
C4
CCL
=
1.551
2.288
1.551
2.288
1.551
2.288
1.659
2.134
1.1 V
V
CCL
1.1 V
V
CCL
=
C4L
=
C4L
1.927
2.194
1.927
2.194
1.927
2.194
2.031
2.045
0.9 V
V
Stratix III Device Handbook, Volume 2
0.9 V
V
CCL
CCL
=
=
1.411
2.277
1.411
2.277
1.411
2.277
1.604
2.042
1.1 V
V
1.1 V
V
I3
CCL
CCL
I3
=
=
1.1 V
V
1.858
2.567
1.858
2.567
1.858
2.567
1.739
2.260
1.1 V
V
CCL
I4
CCL
I4
=
=
1.1 V
V
CCL
1.524
2.345
1.524
2.345
1.524
2.345
1.674
2.147
1.1 V
V
1–271
CCL
=
I4L
=
I4L
0.9 V
V
CCL
1.966
2.245
1.966
2.245
1.966
2.245
2.075
2.091
0.9 V
V
=
CCL
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns