DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 205

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–101. EP3SE50 Column Pins Input Timing Parameters (Part 4 of 4)
Table 1–102. EP3SE50 Row Pins Input Timing Parameters (Part 1 of 3)
© July 2010 Altera Corporation
3.0-V |
PCI-X
3.3-V LVTTL
3.3-V
LVCMOS
3.0-V LVTTL
3.0-V
LVCMOS
2.5 V
1.8 V
Standard
Standard
I/O
I/O
GCLK
GCLK
Clock
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
PLL
PLL
PLL
PLL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Table 1–102
standards.
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
h
h
h
h
h
h
Industrial
Industrial
-0.754
-1.048
0.881
1.301
-0.896
-0.703
-0.896
-0.703
-0.902
-0.697
-0.902
-0.697
-0.890
-0.709
-0.869
-0.859
1.009
0.952
1.009
0.952
1.015
0.946
1.015
0.946
1.003
0.958
0.890
0.986
Fast Model
Fast Model
lists the EP3SE50 row pins input timing parameters for single-ended I/O
Commercial
Commercial
-0.753
-1.048
0.880
1.301
-0.926
-0.700
-0.926
-0.700
-0.937
-0.689
-0.937
-0.689
-0.930
-0.696
-0.907
-0.896
1.052
0.960
1.052
0.960
1.063
0.949
1.063
0.949
1.056
0.956
0.886
1.035
-1.062 -1.167 -1.373 -1.328 -1.604 -1.167 -1.373 -1.328 -1.604
-1.465 -1.595 -1.829 -1.771 -2.037 -1.595 -1.829 -1.771 -2.037
1.240
1.835
1.1 V
V
-1.311 -1.433 -1.658 -1.605 -1.896 -1.451 -1.663 -1.612 -1.927
-1.311 -1.433 -1.658 -1.605 -1.896 -1.451 -1.663 -1.612 -1.927
-1.311 -1.433 -1.658 -1.605 -1.896 -1.451 -1.663 -1.612 -1.927
-1.308 -1.434 -1.661 -1.608 -1.899 -1.450 -1.668 -1.617 -1.932
-1.308 -1.434 -1.661 -1.608 -1.899 -1.450 -1.668 -1.617 -1.932
-1.317 -1.447 -1.676 -1.623 -1.914 -1.459 -1.678 -1.627 -1.942
-1.272 -1.388 -1.573 -1.523 -1.797 -1.395 -1.573 -1.526 -1.829
-1.248 -1.356 -1.505 -1.455 -1.729 -1.364 -1.508 -1.461 -1.764
1.597
1.494
1.597
1.494
1.491
1.600
1.491
1.500
1.591
1.500
1.510
1.458
1.510
1.534
1.434
1.613
C2
CCL
1.1 V
V
C2
CCL
=
=
1.368
2.011
1.1 V
V
1.816
1.640
1.816
1.640
1.641
1.815
1.641
1.654
1.802
1.654
1.730
1.596
1.730
1.762
1.564
1.863
C3
CCL
1.1 V
V
C3
CCL
=
=
1.594
2.291
1.1 V
V
1.931
1.888
1.931
1.888
1.891
1.928
1.891
1.906
1.913
1.906
1.876
1.807
1.876
1.944
1.739
2.103
C4
CCL
1.1 V
V
C4
CCL
=
=
1.537
2.206
1.1 V
V
1.813
1.819
1.813
1.819
1.822
1.810
1.822
1.837
1.795
1.837
1.758
1.742
1.758
1.826
1.674
1.985
CCL
1.1 V
V
CCL
=
=
C4L
C4L
1.814
2.483
0.9 V
V
1.843
2.111
1.843
2.111
2.114
1.840
2.114
2.129
1.825
2.129
1.788
2.015
1.788
1.856
1.947
2.015
CCL
0.9 V
V
Stratix III Device Handbook, Volume 2
CCL
=
=
1.368
2.011
1.1 V
V
1.809
1.667
1.809
1.667
1.666
1.810
1.666
1.675
1.801
1.675
1.729
1.614
1.729
1.760
1.583
1.856
CCL
1.1 V
I3
V
I3
CCL
=
=
1.594
2.291
1.1 V
V
1.936
1.903
1.936
1.903
1.908
1.931
1.908
1.918
1.921
1.918
1.881
1.817
1.881
1.946
1.752
2.101
CCL
1.1 V
I4
V
I4
CCL
=
=
1.537
2.206
1.1 V
V
1.818
1.836
1.818
1.836
1.841
1.813
1.841
1.851
1.803
1.851
1.762
1.754
1.762
1.827
1.689
1.982
CCL
1.1 V
1–205
V
CCL
=
=
I4L
I4L
1.814
2.483
0.9 V
V
1.895
2.144
1.895
2.144
2.149
1.890
2.149
2.159
1.880
2.159
1.840
2.048
1.840
1.905
1.983
2.060
CCL
0.9 V
V
CCL
=
=
Units
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns