MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1036

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

PCI Bus Interface

Figure 17-51

Figure 17-52

A PCI transaction may be terminated by either the initiator or the target. The initiator is ultimately

responsible for concluding all transactions, regardless of the cause of the termination. All transactions are

concluded when PCI_FRAME and PCI_IRDY are both negated, indicating the bus is idle.

Normally, a master initiates termination by negating PCI_FRAME and asserting PCI_IRDY. This

indicates to the target that the final data phase is in progress. The final data transfer occurs when both

PCI_TRDY and PCI_IRDY are asserted. The transaction is considered complete when data is transferred

Transaction Termination

illustrates a PCI single-beat write transaction.

illustrates a PCI burst write transaction.

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Master-Initiated Termination

Figure 17-51. PCI Single-Beat Write Transaction

Figure 17-52. PCI Burst Write Transaction

Byte Enables 1 Byte Enables 2

Byte Enables

Byte Enables 3

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