MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1090

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
Table 18-26
18.3.6.5
Together with the other PCI Express error capture registers, PEX_ERR_CAP_R0 allows vital error
information to be captured when an error occurs. Different error information is reported depending on
whether the error source is from an outbound transaction from an internal source or from an inbound
transaction from an external source; the source of the captured error is reflected in
PEX_ERR_CAP_STAT[GSID]. Note that after the initial error is captured, no further capturing is
performed until the PEX_ERR_CAP_STAT[ECV] bit is clear.
PEX_ERR_CAP_R0 for the case when the error is caused by an outbound transaction from an internal
source (that is, PEX_ERR_CAP_STAT[GSID] ≠ 0h02), is shown in
18-36
26–30 GSID Global source ID. This field indicates the internal platform global source ID that the error transaction
0–24
Bits
25
31
Offset 0xE28
Reset
Name
W
ECV
R
TO
describes the fields of the PCI Express error capture status register.
—
PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
Table 18-26. PCI Express Error Capture Status Register Field Descriptions
Figure 18-28. PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0)
Reserved
Transaction originator. This field Indicates whether the originator of the transaction is from
PEX_CONFIG_ADDR/PEX_CONFIG_DATA.
1 Transaction originated from PEX_CONFIG_ADDR/PEX_CONFIG_DATA.
0 Transaction not originated from PEX_CONFIG_ADDR/PEX_CONFIG_DATA.
originates. This field only applies to non PEX_CONFIG_ADDR/PEX_CONFIG_DATA transactions.
00000
00001
00010
00011
00111
01010
10000
10001
10101
11000
11010
All other settings reserved.
Error capture valid. This bit indicates that the capture registers 0-3 contain valid info. This bit when
set indicates that the captured registers contain valid capturing information. No new capturing will be
done unless this bit is cleared by writing a 1 to it.
PCI
PCI Express 2
PCI Express 1
PCI Express 3
Security
Boot sequencer
Processor instruction
Processor data
DMA
eTSEC1
eTSEC3
Internal Source, Outbound Transaction
—
All zeros
Description
15 16 17 18
FMT
TYPE
Figure
22 23
18-28.
Access: Read/Write
Freescale Semiconductor
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31