MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 589

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

interrupt, if there are no other interrupts queued from that channel, then the channel done interrupt is

negated. If other interrupts remain in the queue, the controller negates the interrupt for one cycle and then

re-asserts it again. Interrupts are queued separately for each channel.

The SEC generates a single interrupt to the MPC8544E embedded programmable interrupt controller

(PIC). See the Programmable Interrupt Controller (PIC) chapter for additional information on the PIC. The

user allows interrupts from the SEC to be reported to the CPU by clearing the mask bit in the associated

vector/priority register of the PIC.

The controller registers are described in detail in the following sections.

The EUASR, displayed in

channel. When an EU is already assigned, it is inaccessible to any other channel.

A four-bit field (see

Freescale Semiconductor

Offset 0x3_1028

Offset 0x0104 (OR0)

Controller Registers

EU Assignment Status Register (EUASR)

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Figure 12-79. EU Assignment Status Register (EUASR)

12-59) indicates the channel to which an EU is assigned.

Table 12-59. Channel Assignment Value

12-79, is used to check the assignment status of an EU to a particular

No channel assigned

Security Engine (SEC) 2.1

Access: Read