MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 361

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

The memory error interrupt enable register, shown in

select error interrupts. When an enabled interrupt condition occurs, the internal int signal is asserted to the

programmable interrupt controller (PIC).

Freescale Semiconductor

Offset 0xE48

MBED Multiple-bit ECC error disable

MSED Memory select error disable

ACED Automatic calibration error disable

SBED Single-bit ECC error disable

describes the ERR_DISABLE fields.

Memory Error Interrupt Enable (ERR_INT_EN)

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

0 Automatic calibration errors are enabled.

1 Automatic calibration errors are disabled.

0 Multiple-bit ECC errors are detected if DDR_SDRAM_CFG[ECC_EN] is set. They are reported if

1 Multiple-bit ECC errors are not detected or reported.

0 Single-bit ECC errors are enabled.

1 Single-bit ECC errors are disabled.

0 Memory select errors are enabled.

1 Memory select errors are disabled.

ERR_INT_EN[MBEE] is set. Note that uncorrectable read errors cause the assertion of core_fault_in ,

which causes the core to generate a machine check interrupt, unless it is disabled (by clearing

HID1[RFXE]). If RFXE is zero and this error occurs, MBED and ERR_INT_EN[MBEE] must be zero and

ECC_EN must be one to ensure that an interrupt is generated.

Figure 9-28. Memory Error Interrupt Enable Register (ERR_INT_EN)

Table 9-32. ERR_DISABLE Field Descriptions

9-28, enables ECC interrupts or memory

MBEE SBEE — MSEE

DDR Memory Controller

Access: Read/Write