MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 845

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 15-107
15.5.3.10 Lossless Flow Control Configuration Registers
When enabled via RCTRL[LFC], the eTSEC will track location of the last free BD in each Rx BD ring via
the value of RFBPTRn. Using this pointer and the ring length stored in RQPRMn[LEN], the eTSEC will
continuously calculate the number of free BDs in the ring. Whenever the calculated number of free BDs
in the ring drops below the pause threshold specified in RQPRMn[FBTHR], the eTSEC will issue link
layer flow control. It will continue to assert flow control until the free BD count for each active ring
reaches or exceeds RQPRMn[FBTHR]. See
Buffers,”
15.5.3.10.1 Receive Queue Parameters 0–7 (RQPRM0–PQPRM7)
The RQPRMn registers specify the minimum number of BDs required to prevent flow control being
asserted and the total number of Rx BDs in their respective ring. Whenever the free BD count calculated
by the eTSEC for any active ring drops below the value of RQPRMn[FBTHR] for that ring, link level flow
control will be asserted. Software must not write to RQPRMn while LFC is enabled and the eTSEC is
actively receiving frames. However, software may modify these registers after disabling LFC by clearing
RCTRL[LFC]. Note that packets may be lost due to lack of RxBDs while RCTRL[LFC] is clear. Software
can prevent packet loss by manually generating pause frames (via TCTRL[TFC_PAUSE]) to cover the
time when RCTRL[LFC] is clear.
Freescale Semiconductor
Offset eTSEC1:0x2_4BFC; eTSEC3:0x2_5BFC
Reset
13–15
16–17
18–25
26–31
2–12
Bits
0–1
W
R
0
for the theory of operation of these registers.
—
Name
1
EL
—
—
—
—
EI
describes the fields of the ATTRELI register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2
Reserved
Extracted length. Specifies the number of bytes, as a multiple of 8 bytes, to extract from the receive
frame. The DMA controller uses this field to perform extraction. If set to zero, no extraction is
performed.
To ensure that EL is a multiple of 8 bytes, these bits should be written with zero.
Reserved
Extracted index. Points to the first byte, as a multiple of 64 bytes, within the receive frame from which
to begin extracting data.
To ensure that EI is a multiple of 8 bytes, these bits should be written with zero.
EL
Figure 15-104. ATTRELI Register Definition
Table 15-107. ATTRELI Field Descriptions
Figure 15-105
Section 15.6.6.1, “Back Pressure Determination via Free
12 13
describes the definition for the RQPRMn register.
All zeros
—
Description
17 18
Enhanced Three-Speed Ethernet Controllers
EI
25 26
Access: Read/Write
—
15-113
31