MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 662

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MPC8544COMEDEV

Manufacturer Part Number
MPC8544COMEDEV
Description
KIT DEV EXPRESS MPC8544COM
Manufacturer
Freescale Semiconductor
Type
MPUr
Datasheets

Specifications of MPC8544COMEDEV

Contents
Board
For Use With/related Products
MPC8544
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Local Bus Controller
When TRLX and CSNT are set in a write access, the LWE[0:3] strobe signals are negated one clock earlier
than in the normal case, as shown in
one clock earlier.
14-42
Figure 14-27. GPCM Relaxed Timing Back-to-Back Writes (XACS = 0, ACS = 1x, SCY = 0,
LBCTL
LCS n
LWE n
LALE
LCLK
LAD
LOE
TA
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
A
LBCTL
LCLK
LCS n
LWE n
LALE
LAD
LOE
Address 1
TA
A
Address
(XACS = 0, ACS = 10, SCY = 0, CSNT = 1, TRLX = 1)
Figure 14-28. GPCM Relaxed Timing Write
Latched Address 1
Figure 14-28
Write Data 1
ACS = 10
CSNT = 0, TRLX = 1)
Latched Address
Write Data
ACS = 10
and
ACS = 11
Figure
CSNT = 1
14-29. If ACS ≠ 00, LCSn is also negated
Address 2
Latched Address 2
Write Data 2
Freescale Semiconductor

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