MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 450

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller
MSIIR[SRS] selects the associated MSIR and MSIIR[IBS] selects the interrupt flag/bit in that register that
is to be set. The corresponding interrupt needs to be unmasked for the interrupt to occur. A read to an MSIR
clears the all of its flags.
10.4.6
Whenever the PCI Express controller is in root complex mode and it receives an inbound INTx asserted
or negated message transaction, it asserts or negates an equivalent internal INTx signal to the PIC. This
INTx virtual-wire interrupt signaling mechanism replaces the PCI standard sideband interrupts (INTA,
INTB, INTC, and INTD) that historically were connected to the IRQn external interrupt inputs. The
internal INTx signals from the PCI Express controller are logically combined with the interrupt request
(IRQn) signals so that they share the same OpenPIC external interrupt controlled by the associated
EIVPRn and EIDRn registers.
Table 10-52
In general, these signals should be considered mutually exclusive. In particular, if an IRQn signal is being
used as active high (EIVPRn[P] = 1), or edge triggered (EIVPRn[S] = 0), the system must not allow
inbound PCI Express INTx transactions.
If a PCI Express INTx signal is being used, the PIC must be configured so that external interrupts are active
low (EIVPRn[P] = 0) and level sensitive (EIVPRn[S] = 1). In this case, the associated IRQn should be
pulled high. Note that it is possible to share IRQn and INTx if the external interrupt is also active-low and
level sensitive. However, if an interrupt occurs, the interrupt service routine must poll both the external
sources connected to the IRQn input and the PCI Express INTx sources to determine from which path the
external interrupt came.
10.4.7
There are appropriate clock prescalers and synchronizers to provide a time base for the four internal timers
of the PIC unit. The timers can be individually programmed to generate a processor interrupt when they
10-52
details the association of INTx signals to IRQn signals.
PCI Express INTx
Global Timers
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 10-52. PCI Express INTx/IRQ n Sharing
PCI Express Number INTx
PCI Express 1
PCI Express 2
PCI Express 3
INTC IRQ2
INTD IRQ3
INTC IRQ6
INTD IRQ7
INTC IRQ10
INTD IRQ11
INTB IRQ1
INTB IRQ5
INTB IRQ9
INTA
INTA
INTA
IRQ n
IRQ0
IRQ4
IRQ8
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