MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 323

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

e500 Coherency Module
EEBPCR[CPU_PRI] specifies the priority level associated with all e500 core initiated transactions. This
value allows users running time-critical applications to adjust the average response latency of transactions
initiated by the core compared to those initiated by I/O masters. This priority level affects whether e500
core requests can interrupt the streaming of address tenures initiated by (the ECM on behalf of) I/O
masters. Only transactions with a priority greater than the current CCB transaction can interrupt streaming.
The higher the core’s priority, the lower the average latency needed for it to obtain bus grants from the
ECM, because it can interrupt lower priority streaming. The default value of zero gives all core-initiated
transactions the lowest priority, which prevents the core from interrupting I/O master transaction streams.
EEBACR[A_STRM_CNT] allows users to balance response latency with throughput and should prove
useful in tuning systems with multiple time-critical tasks. The default value of 0b11 causes the ECM to
attempt to stream as many as four transactions initiated from the same CCB master. Increasing this value
increases the maximum number of transactions that may be streamed together from any one CCB master.
Raising this value can increase throughput for high priority transactions, but may increase latency for
lower priority transactions from another CCB master. Note that the e500 core must also have streaming
enabled (through HID1[ASTME]) for the CCB to stream.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor
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