MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 204

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Core Complex Overview
5.7
The core complex contains separate 32-Kbyte, eight-way set-associative, level 1 (L1) instruction and data
caches to give rapid access to instructions and data.
The data cache supports four-state MESI memory coherency protocol. The core complex broadcasts all
cache management functions based on the setting of the address broadcast enable bit, HID1[ABE],
allowing management of other caches in the system.
The caches implement a pseudo-least-recently-used (PLRU) replacement algorithm.
Parity generation and checking may be enabled for both caches, and each cache can be independently
invalidated through L1CSR1 and L1CSR0. Additionally, instructions are provided to perform cache
locking and unlocking on both data and instruction caches on a cache-block granularity. These are listed
in
Individual instruction cache blocks and data cache blocks can be invalidated using the icbi and dcbi
instructions, respectively. The entire data cache can be invalidated by setting L1CSR0[CFI]; the entire
instruction cache can be invalidated by setting L1CSR1[ICFI].
5.8
The e500 core supports an extended exception handling model, with nested interrupt capability and
extensive interrupt vector programmability. The following sections define the exception model, including
an overview of exception handling as implemented on the e500 core, a brief description of the exception
classes, and an overview of the registers involved in the processes.
5.8.1
In general, interrupt processing begins with an exception that occurs due to external conditions, errors, or
program execution problems. When the exception occurs, the processor checks to verify interrupt
processing is enabled for that particular exception. If enabled, the interrupt causes the state of the processor
to be saved in the appropriate registers and prepares to begin execution of the handler located at the
associated vector address for that particular exception.
Once the handler is executing, the implementation may need to check one or more bits in the exception
syndrome register (ESR) or the SPEFSCR, depending on the exception, to verify the specific cause of the
exception and take appropriate action.
The core complex provides the interrupts described in
5-18
Section 5.10.3, “Cache Control Instructions.”
On-Chip Cache Implementation
Interrupts and Exception Handling
Exception Handling
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Section 5.8.5, “Interrupt Registers.”
Freescale Semiconductor