MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 192
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MPC8544COMEDEV
Manufacturer Part Number
MPC8544COMEDEV
Description
KIT DEV EXPRESS MPC8544COM
Manufacturer
Freescale Semiconductor
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544COMEDEV
Contents
Board
For Use With/related Products
MPC8544
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 192 of 1340
- Download datasheet (12Mb)
Core Complex Overview
5-6
•
•
•
•
•
The e500 register set is modified as follows:
Cache structure—Separate 32-Kbyte, 32-byte line, 8-way set-associative level 1 instruction and
data caches
— 1.5-cycle cache array access, 3-cycle load-to-use latency
— Pseudo-LRU (PLRU) replacement algorithm
— Copy-back data cache that can function as a write-through cache on a page-by-page basis
— Supports all embedded category memory coherency modes
— Supports EIS-defined cache-locking instructions, as listed in
Dual-issue superscalar control
— Two-instructions-per-clock peak issue rate
— Precise exception handling
Decode unit
— 12-entry instruction queue (IQ)
— Full hardware detection of interlocks
— Decodes as many as two instructions per cycle
— Decode serialization control
— Register dependency resolution and renaming
Branch prediction unit (BPU)
— Dynamic branch prediction using a 512-entry, 4-way set-associative branch target buffer
— Branch prediction is handled in the fetch stages.
– GPRs are widened to 64 bits to support 64-bit load, store, and merge operations. Note that
– A 64-bit accumulator (ACC) has been added.
– The signal processing and embedded floating-point status and control register (SPEFSCR)
These registers are shown in
– Single-cycle integer add and subtract with the same latencies for SPE operations as for the
– Single-cycle logical operations
– Single-cycle shift and rotates
– Four-cycle integer pipelined multiplies
– 4-, 11-, 19-, and 35-cycle integer divides
– If rA or rB is zero, a floating-point divide takes 4 cycles; all other cases take 29 cycles.
– Four-cycle SIMD pipelined multiply-accumulate (MAC)
– 64-bit accumulator for no-stall MAC operations
– 64-bit loads and stores
– 64-bit merge instructions
(BTB) supported by the e500 BTB instructions listed in
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
the upper 32 bits are affected only by 64-bit instructions.
provides interrupt control and status for SPE and embedded floating-point instructions.
32-bit equivalent
Figure
5-7. SPE instructions are grouped as follows:
Table
Table 5-3
5-5.
Freescale Semiconductor
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