MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 523

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 12-21
12.4.3.3
This value indicates the number of bytes of key memory that should be used in performing S-box
permutation. Any key data beyond the number of bytes in the key size register is ignored. This register is
cleared when the AFEU is reset or re-initialized. If the key size specified is less than 1 or greater than 16,
a key size error is generated. If the key size register is modified during processing, a context error is
generated. Note: Although the AFEU supports key lengths as short as 1 byte, a 1 byte key offers little
security. Most uses of ARC-4 specify keys of 5–16 bytes.
Figure 12-22
Freescale Semiconductor
The following bits are described for information only. They are not under direct user control.
The following bits are controlled through the MODE0 field of the descriptor header.
Address AFEU 0x3_8008
56–60
0–55
Bits
61
62
63
Reset
W
R
Name
0
CS
DC
—
—
PP
describes AFEU mode register fields.
AFEU Key Size Register (AFEUKSR)
depicts the AFEU key size register.
Reserved
Reserved
Context source. If set, this causes the context to be moved from the input FIFO into the S-box prior to starting
encryption/decryption. Otherwise, context should be directly written to the context registers. Context source is
only checked if the prevent permute bit is set.
0 Context not from FIFO
1 Context from input FIFO
Dump context. If set, this causes the context to be moved from the S-box to the output FIFO following assertion
AFEU’s done interrupt.
0 Do not dump context
1 After cipher, dump context
Prevent permute. Normally, the AFEU receives a key and uses that information to randomize the S-box. If
re-using a context from a previous descriptor, this bit should be set to prevent AFEU from re-performing this
permutation step.
0 Perform S-box permutation
1 Do not permute
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 12-21. AFEU Mode Register Field Descriptions
Figure 12-22. AFEU Key Size Register
—
All zeros
Description
51 52
Security Engine (SEC) 2.1
Access: Read-only
KEY SIZE
12-43
63