MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 190
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MPC8544COMEDEV
Manufacturer Part Number
MPC8544COMEDEV
Description
KIT DEV EXPRESS MPC8544COM
Manufacturer
Freescale Semiconductor
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544COMEDEV
Contents
Board
For Use With/related Products
MPC8544
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 190 of 1340
- Download datasheet (12Mb)
Core Complex Overview
independent vector floating-point add instructions can be issued and completed with a throughput of one
instruction per cycle.
The core complex includes independent on-chip, 32-Kbyte, eight-way set-associative, physically
addressed caches for instructions and data. It also includes on-chip first-level instruction and data memory
management units (MMUs) and an on-chip second-level unified MMU.
The core complex allows cache-line-based user-mode locks on the contents in either the instruction or data
cache. This provides embedded applications with the capability for locking interrupt routines or other
important (time-sensitive) instruction sequences into the instruction cache. It also allows data to be locked
into the data cache, which supports deterministic execution time.
The core complex supports a high-speed on-chip internal bus with data tagging called the core complex
bus (CCB). The CCB has two general-purpose read data buses, one write data bus, data parity bits, data
tag bits, an address bus, and address attribute bits. The processor core complex supports out-of-order reads,
in-order writes, and one level of pipelining for addresses with address-retry responses. It can also support
single-beat and burst data transfers for memory accesses and memory-mapped I/O operations.
5.2
Table
(SVR). These registers can be accessed as SPRs through the e500 core (see
Version Register (PVR),”
registers defined by the integrated device (see
and
5-4
•
•
Section 19.4.1.17, “System Version Register
MPC8544E Revision
5-1lists the revision codes in the processor version register (PVR) and the system version register
The first-level MMUs contain two four-entry, fully-associative instruction and data translation
lookaside buffer (TLB) arrays that provide support for demand-paged virtual memory address
translation and variable-sized pages. They also contain two 64-entry, 4-way set-associative
instruction and data TLB arrays that support 4-Kbyte pages. These arrays are maintained entirely
by the hardware with a true least-recently-used (LRU) algorithm.
The second-level MMU contains a 16-entry, fully-associative unified (instruction and data) TLB
array that provides support for variable-sized pages. It also contains a unified TLB for 4-Kbyte
page size support, as follows:
— a 256-entry, 2-way set-associative unified TLB for the e500v1
— a 512-entry, 4-way set-associative unified TLB for the e500v2
These second-level TLBs are maintained completely by the software.
e500 Processor and System Version Numbers
1.0
1.1
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
and
Revision
Table 5-1. Device Revision Level Cross-Reference
Core
2.1
2.2
Section 6.5.4, “System Version Register
Processor Version
Register (PVR)
0x8021_0021
0x8021_0022
“Section 19.4.1.16, “Processor Version Register (PVR),”
(SVR)”).
0x803C_0110 for MPC8544E (with security)
0x8034_0110 for MPC8544 (without security)
0x803C_0111 for MPC8544E (with security)
0x8034_0111 for MPC8544 (without security)
(SVR)”) or as memory-mapped
System Version
Section 6.5.3, “Processor
Register (SVR)
Freescale Semiconductor
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