MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 713

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MPC8544COMEDEV

Manufacturer Part Number
MPC8544COMEDEV
Description
KIT DEV EXPRESS MPC8544COM
Manufacturer
Freescale Semiconductor
Type
MPUr
Datasheets

Specifications of MPC8544COMEDEV

Contents
Board
For Use With/related Products
MPC8544
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
14.5.4.3.8
To allow for very high speeds on the memory bus, the capacitive loading on the local bus must be taken
into consideration as shown in
To implement a system using the hierarchy described earlier for 2 synchronous memory banks, 1 address
latch, and 1 buffer loading the multiplexed address/data bus sees a loading of 4 loads of about 6.5 pF
maximum. For a nominal load, 30 pF can be used.
Freescale Semiconductor
t
EXTERNAL CK
CKE
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
RE
CE
An
W
S
SDRAM Timing
Note:Capacitance values compiled from worst case numbers from
RAS, CAS, WE, CS, CKE, DQM
various data sheets from Samsung and Micron
All banks idle
Figure 14-76. SDRAM Self-Refresh Mode Timing
Table
Self-refresh entry
DQ
Address
Signal
CLK
0
Table 14-42. SDRAM Capacitance
–DQ
14-42.
31
Self-refresh exit
Stable clock
Min
2.0
2.0
2.0
3.5
Max
4.0
5.0
5.0
6.5
Supplier-specific
minimum time
New command
can occur here
Unit
NOP
pf
pf
pf
pf
Local Bus Controller
14-93

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