MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 752

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
15-20
0x2_4744–
0x2_46CC RUND—Receive undersize packet counter
0x2_46DC RDRP—Receive drop counter
0x2_46D0 ROVR—Receive oversize packet counter
0x2_46D4 RFRG—Receive fragments counter
0x2_46D8 RJBR—Receive jabber counter
0x2_46EC TBCA—Transmit broadcast packet counter
0x2_46FC TSCL—Transmit single collision packet counter
0x2_470C TNCL—Transmit total collision counter
0x2_471C TFCS—Transmit FCS error counter
0x2_472C TFRG—Transmit fragments frame counter
0x2_473C CAM2—Carry register two mask register
0x2_47FC
0x2_46E0 TBYT—Transmit byte counter
0x2_46E4 TPKT—Transmit packet counter
0x2_46E8 TMCA—Transmit multicast packet counter
0x2_46F0 TXPF—Transmit PAUSE control frame counter
0x2_46F4 TDFR—Transmit deferral packet counter
0x2_46F8 TEDF—Transmit excessive deferral packet counter
0x2_4700 TMCL—Transmit multiple collision packet counter
0x2_4704 TLCL—Transmit late collision packet counter
0x2_4708 TXCL—Transmit excessive collision packet counter
0x2_4710 Reserved
0x2_4714 TDRP—Transmit drop frame counter
0x2_4718 TJBR—Transmit jabber frame counter
0x2_4720 TXCF—Transmit control frame counter
0x2_4724 TOVR—Transmit oversize frame counter
0x2_4728 TUND—Transmit undersize frame counter
0x2_4730 CAR1—Carry register one register
0x2_4734 CAR2—Carry register two register
0x2_4738 CAM1—Carry register one mask register
0x2_4740 RREJ*—Receive filer rejected packet counter
eTSEC1
Offset
Reserved
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
eTSEC Counter Control and TOE Statistics Registers
Table 15-4. Module Memory Map (continued)
Name
3
1
3
eTSEC Transmit Counters
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
R
R
2
0xFE03_FFFF
0x000F_FFFD
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
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