MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1063

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.3.2
18.3.2.1
The PCI Express configuration address register, shown in
accesses to PCI Express internal and external configuration registers.
Freescale Semiconductor
0xDF4–
0xE14–
0xE38–
0x000–
0x000–
0xDFC
0xE0C
0xE1C
0xE2C
0xFFC
0xFFC
0xFFC
Offset
0xE00
0xE04
0xE08
0xE10
0xE20
0xE24
0xE28
0xE30
0xE34
Offset 0x000
Reset
Reserved
PEX_ERR_DR—PCI Express error detect register
Reserved
PEX_ERR_EN—PCI Express error interrupt enable register
Reserved
PEX_ERR_DISR—PCI Express error disable register
Reserved
PEX_ERR_CAP_STAT—PCI Express error capture status register
Reserved
PEX_ERR_CAP_R0—PCI Express error capture register 0
PEX_ERR_CAP_R1—PCI Express error capture register 1
PEX_ERR_CAP_R2—PCI Express error capture register 2
PEX_ERR_CAP_R3—PCI Express error capture register 3
Reserved
PCI Express Controller 2 registers
Note: All registers defined for PCI Express Controller 1 are also defined for PCI Express Controller 2; the offsets
PCI Express Controller 3 registers
Note: All registers defined for PCI Express Controller 1 are also defined for PCI Express Controller 3; the offsets
W
R
PCI Express Configuration Access Registers
Figure 18-2. PCI Express Configuration Address Register (PEX_CONFIG_ADDR)
PCI Express Configuration Address Register (PEX_CONFIG_ADDR)
EN
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
PCI Express Controller 3 Memory-Mapped Registers—Block Base Address 0x0_B000
PCI Express Controller 2 Memory-Mapped Registers—Block Base Address 0x0_9000
of PCI Express Controller 2 registers are the same except they have a different block base address.
of PCI Express Controller 3 registers are the same except they have a different block base address.
1
Table 18-3. PCI Express Memory-Mapped Register Map (continued)
—
3
4
EXTREGN
7
PCI Express Error Management Registers
Register
8
BUSN
All zeros
15 16
Figure
DEVN
18-2, contains address information for
20 21
Access
Mixed
R/W
R/W
R/W
R/W
R/W
R/W
w1c
FUNCN
—
—
—
—
—
—
23 24
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
PCI Express Interface Controller
Reset
—
—
—
—
—
—
Access: Read/Write
REGN
18.3.6.1/18-29
18.3.6.2/18-32
18.3.6.3/18-34
18.3.6.4/18-35
18.3.6.5/18-36
18.3.6.6/18-38
18.3.6.7/18-39
18.3.6.8/18-40
Section/Page
29 30 31
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—
—
—
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18-9