MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1211

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

PMC1–PMC9, shown in

the 64 reference events that can be counted on all of these registers.

This section describes the use of some features of the performance monitor.

PMCs can generate an interrupt on an overflow when the msb of a counter changes from 0 to 1. For the

interrupt to be signalled, the condition enable bit (PMLCAn[CE]) and performance monitor interrupt

enable bit (PMGC0[PMIE]) must be set. When an interrupt is signalled and the

freeze-counters-on-enabled-condition-or-event bit (PMGC0[FCECE]) is set, PMGC0[FAC] is set by

hardware and all of the registers are frozen. Software can clear the interrupt condition by resetting the

performance monitor and clearing the most significant bit of the counter that generated the overflow.

Freescale Semiconductor

Offset 0xE_1028

Functional Description

describes PMC0 fields.

describes PMCn fields.

Performance Monitor Interrupt

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Figure 20-8. Performance Monitor Counter Register (PMC1–PMC9)

Event count. An overflow is indicated when the msb = 1. Manually setting the msb can

cause an immediate interrupt.

Event count. Counts only clock cycles

20-8, are 32-bit counters that can monitor 64 unique events in addition to

Table 20-8. PMC[1–9] Field Descriptions

Table 20-7. PMC0 Field Descriptions

Device Performance Monitor

Access: Read/Write