MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 237

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Freescale Semiconductor

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Exception Syndrome Register (ESR)

IVOR16–IVOR31

IVOR36–IVOR63

Reserved, should be cleared.

Illegal instruction exception

Privileged instruction exception

Trap exception

Reserved and permanently cleared because the e500 does not implement this FPU.

Setting it has no effect.

Store operation

Figure 6-22. Exception Syndrome Register (ESR)

PTR — ST — DLK

Table 6-11. IVOR Assignments (continued)

Table 6-12. ESR Field Descriptions

Fixed-interval timer interrupt

Watchdog timer interrupt

Data TLB error

Instruction TLB error

Reserved for future architectural use

SPE unavailable

Floating-point data exception

Floating-point round exception

Performance monitor

Allocated for implementation-dependent use

Interrupt Type

Access: Supervisor read/write

Core Register Summary

Alignment, data

storage, data TLB

Interrupt Types