MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 915

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Other information about the link is also returned.(Extend Status, No pre, Remote Fault, An Ability, Link status, extend Ability)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
(Uses the PHY address (0) and Register address (1) placed in MIIMADD register),
Table 15-150. MII Mode Register Initialization Steps (continued)
read the MIIMSTAT register and check bit 10 (AN Done and Link is up)
RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
TBASE0–TBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Initialize (Empty) Receive Descriptor ring and fill with empty buffers
MACnADDR1/2[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize (Empty) Transmit Descriptor ring and fill buffers with Data
MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0100]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]
DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]
GADDR n [0000_0000_0000_0000_0000_0000_0000_0000]
Check auto-negotiation attributes in the PHY as necessary.
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
Perform an MII Mgmt read cycle of Status Register.
Initialize MACnADDR1/2 (Optional)
Clear MIIMCOM[Read Cycle].
Initialize DMACTRL (Optional)
Initialize GADDR n (Optional)
Initialize RBASE0–RBASE7,
Set MIIMCOM[Read Cycle].
Initialize TBASE0–TBASE7,
Initialize RCTRL (Optional)
When MIIMIND[BUSY]=0,
Initialize IMASK (Optional)
Enable Transmit Queues
Enable Receive Queues
Clear IEVENT register,
Enable Rx and Tx,
Initialize RQUEUE
Initialize TQUEUE
Enhanced Three-Speed Ethernet Controllers
15-183